-[[!tag standards]]
-
# Simple-V Compliancy Levels
The purpose of the Compliancy Levels is to provide a documented
Levels (SFS, SFFS, Linux, AIX). They are separate and independent. It
is perfectly fine to implement Ultra-Embedded on AIX, and perfectly fine to implement 3D/Advanced on SFS. **Compliance with SV Levels does not convey or remove the obligation of Compliance with SFS/SFFS/Linux/AIX Levels and vice-versa**.
-# Zero-Level
+## Zero-Level
This level exists to indicate the critical importance of all and any
features attempted to be executed on hardware that has no support at
it is absolutely critical to have all capabilities of Simple-V sit
within full Illegal Instruction space of existing and future Hardware.
-# Ultra-Embedded Level
+## Ultra-Embedded Level
This level exists as an entry-level into SVP64, most suited to resource
constrained soft cores, or Hardware implementations where unit cost is a much
Scalar non-prefixed, i.e. as if the Prefix had not been present.
Additionally all SV SPRs must be zero and the 24-bit `RM` field must be zero.
-# Embedded Level
+## Embedded Level
This level is more suitable for Hardware implementations where performance and power saving begins to matter. A second instruction, `svstep`, used
by Vertical-First Mode, is required, as is hardware-level looping in
instructions are Prefixed
to 64-bit.
-# DSP / Audio / Video Level
+## DSP / Audio / Video Level
This level is best suited to high-performance power-efficient but
specialist Compute workloads. 128 GPRs, FPRs and CR Fields are all
workloads it is strongly recommended. Matrix (Dimensional) REMAP
and Swizzle may also be useful to help with 24-bit (3 byte) Structured Audio Streams and are also recommended but not mandatory.
-# High-end DSP
+## High-end DSP
In this Compliancy Level the benefits of the Offset and Index REMAP
subsystem becomes worth its hardware cost. In lower-performing DSP
and A/V workloads it is not.
-# 3D / Advanced / Supercomputing
+## 3D / Advanced / Supercomputing
This Compliancy Level is for highest performance and energy efficiency.
All aspects of SVP64 must be entirely implemented, in full, in Hardware.
operations. Just as with SRAMs multiple write-enable lines may be
raised to update higher-width elements.
-# Examples
+## Examples
Assuming that hardware implements scalar operations only,
and implements predication but not elwidth overrides:
Illegal Exception is raised, and the Embedded Level requires full
VL Loop support in hardware.
+[[!tag standards]]
+
+-------
+
+\newpage()
+
+