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[libreriscv.git] / openpower / sv / ldst.mdwn

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index eb32548ed1d5ea665dba1f27bf61f394356cb1a1..8562d32c20cdbeaa5d4c2c82e0e964779774e8fd 100644 (file)
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -152,7 +152,13 @@ written out in quick succession to a memory-mapped peripheral from
 sequentially-numbered registers.
 
 Note that any memory location may be Cache-inhibited
-(Power ISA v.1, Book III, 1.6.1, p1033)
+(Power ISA v3.1, Book III, 1.6.1, p1033)
+
+*Programmer's Note: an immediate also with a Scalar source as
+a "VSPLAT" mode is simply not possible: there are not enough
+Mode bits. One single Scalar Load operation may be used instead, followed
+by any arithmetic operation (including a simple mv) in "Splat"
+mode.*
 
 **LD/ST Indexed**