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[libreriscv.git] / openpower / sv / normal.mdwn

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 586c96e9e0812232f6300b12c3e059804788b2e8..4a136b93d2ab949dfc2930063a5804e92b9c5fa1 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -141,7 +141,7 @@ it is also possible to perform prefix-sum (Fibonacci Series) in certain
 circumstances. Details are in the [[svp64/appendix]]
 
 Reduce Mode should not be confused with Parallel Reduction [[sv/remap]].
-As explained in the [[sv/appendix]] Reduce Mode switches off the check
+As explained in the [[sv/svp64/appendix]] Reduce Mode switches off the check
 which would normally stop looping if the result register is scalar.
 Thus, the result scalar register, if also used as a source scalar,
 may be used to perform sequential accumulation. This *deliberately*