(no commit message)

[libreriscv.git] / openpower / sv / normal.mdwn

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index cb260ce218f5edb77fb414729e2f38f4bdfaf258..aeddefd6096f87d30d50bad998d034ce2c25bf2e 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -33,7 +33,8 @@ the following Modes apply to Arithmetic and Logical SVP64 operations:
   for both INT and FP.
 * **reduce mode**. If used correctly, a mapreduce (or a prefix sum)
   is performed. See [[svp64/appendix]].
-  Note that there are comprehensive caveats when using this mode.
+  Note that there are comprehensive caveats when using this mode,
+  and it should not be confused with the Parallel Reduction [[sv/remap]].
 * **pred-result** will test the result (CR testing selects a bit of CR
   and inverts it, just like branch conditional testing) and if the
   test fails it is as if the *destination* predicate bit was zero even