**Proposal: Add the following Definition to Section 1.3.1 of Book I**
-**Definition of SVP64 Prefixing:**
+**Definition of Simple-V:**
-In its simpest form, SVP64 is a 32-bit Prefix conceptually similar to Intel 8086 `REP`
-instruction that both augments its following Defined Word Suffix, and also may
-repeat that instruction with optional sequential register offsets from those given in the
+In its simpest form, the Simple-V Loop/Vector concept is a Prefixing
+system (sililar to the 8086 `REP` instruction) that both augments its
+following Defined Word Suffix, and also may repeat that instruction
+with optional sequential register offsets from those given in the
Suffix. Register numbers may also be extended (larger register files).
-More advanced features add predication, element-width overrides, and Vertical-First
-Mode.
+More advanced features add predication, element-width overrides, and
+Vertical-First Mode.
+
+**Definition of SVP64 Prefixing:**
+
+SVP64 is a well-defined implementation of the Simple-V Loop/Vector concept,
+in a 32-bit Prefix format, that exploits the following instruction
+(the Defined Word) using it as a "template". It requires 24 bits,
+some of which are common to all Suffixes, and some Mode bits are specific
+to the Defined Word class: Load/Store-Immediate, Load/Store-Indexed,
+Arithmetic/Logical, Condition Register operations, and Branch-Conditional.
+Anything not falling into those five categories is termed "UnVectoriseable".
**Definition of Vertical-First:**
-Normal Cray-style Vectorisation, designated Horizontal-First, performs element-level
-operations (often in parallel) before moving in the usual fashion to the next
-instruction. Vertical-First on the other hand executes *one element operation only*
-then moves on to the next instruction, whereupon if that is also an SVP64-Prefixed
-instruction the exact same element offset is used. Element offsets are then explicitly
-advanced by calling a special instruction, `svstep`. The term "Vertical-First"
-stems from visually listing program instructions vertically and register files horizontally.
+Normal Cray-style Vectorisation, designated Horizontal-First, performs
+element-level operations (often in parallel) before moving in the usual
+fashion to the next instruction. Vertical-First on the other hand executes
+*one element operation only* then moves on to the next instruction,
+whereupon if that is also an SVP64-Prefixed instruction the exact same
+element offset is used. Element offsets are then explicitly advanced
+by calling a special instruction, `svstep`. The term "Vertical-First"
+stems from visually listing program instructions vertically and register
+files horizontally.
**Definition of SVP64Single Prefixing:**
-A 32-bit Prefix in front of a Defined Word that extends register numbers
-(allows larger register files), adds single-bit predication, element-width overrides,
-and optionally adds Saturation to Arithmetic instructions that normally would not
-have it. *SVP64 is in Draft only* and is yet to be defined.
+A 32-bit Prefix in front of a Defined Word that extends register
+numbers (allows larger register files), adds single-bit predication,
+element-width overrides, and optionally adds Saturation to Arithmetic
+instructions that normally would not have it. *SVP64 is in Draft only*
+and is yet to be defined.
**Definition of "UnVectoriseable":**
include `sc` or `sync` which have no registers. `mtmsr` is also classed
as UnVectoriseable because there is only one `MSR`.
-UnVectorised instructions are required to be detected as such if
-Prefixed (either SVP64 or SVP64Single) and an Illegal Instruction
-Trap raised.
+UnVectorised instructions are required to be detected as such if Prefixed
+(either SVP64 or SVP64Single) and an Illegal Instruction Trap raised.
-*Architectural Note: Given that a "pre-classification" Decode Phase is
-required (identifying whether the Suffix - Defined Word - is
-Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional),
-adding "UnVectorised" to this phase is not unreasonable.*
+*Architectural Note: Given that a "pre-classification" Decode Phase
+is required (identifying whether the Suffix - Defined Word - is
+Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional), adding
+"UnVectorised" to this phase is not unreasonable.*
# New 64-bit Instruction Encoding spaces
Encoding spaces and their potential are illustrated:
-| Encoding |Available bits|Scalar|Vectoriseable | SVP64Single | PO1-Prefixable |
-|----------|--------------|------|--------------|--------------|----------------|
-|EXT000-063| 32 | yes | yes |yes |yes |
-|EXT100-163| 64 | yes | no |no |not twice |
-|RESERVED2 | 57 | N/A |not applicable|not applicable|not applicable |
-|EXT232-263| 32 | yes | yes |yes |no |
-|RESERVED1 | 32 | N/A | no |no |no |
+| Encoding |Available bits|Scalar|Vectoriseable | SVP64Single |PO1-Prefixable |
+|----------|--------------|------|--------------|--------------|---------------|
+|EXT000-063| 32 | yes | yes |yes |yes |
+|EXT100-163| 64 | yes | no |no |not twice |
+|RESERVED2 | 57 | N/A |not applicable|not applicable|not applicable |
+|EXT232-263| 32 | yes | yes |yes |no |
+|RESERVED1 | 32 | N/A | no |no |no |
Notes:
projects / libreriscv.git / blobdiff