# RFC ls008 SVP64 Management instructions
-[[!tag opf_rfc]]
-
**URLs**:
* <https://libre-soc.org/openpower/sv/>
* <https://libre-soc.org/openpower/sv/rfc/ls008/>
* <https://bugs.libre-soc.org/show_bug.cgi?id=1040>
-* <https://git.openpower.foundation/isa/PowerISA/issues/87>
+* <https://git.openpower.foundation/isa/PowerISA/issues/123>
**Severity**: Major
**Summary**
```
- Instructions added
setvl - Cray-style "Set Vector Length" instruction
svstep - Vertical-First Mode explicit Step and Status
- svremap - Re-Mapping of Register Element Offsets
- svindex - General-purpose setting of SHAPEs to be re-mapped
- svshape - Hardware-level setting of SHAPEs for element re-mapping
- svshape2 - Hardware-level setting of SHAPEs for element re-mapping (v2)
```
**Submitter**: Luke Leighton (Libre-SOC)
**Impact on processor**:
```
- Addition of six new "Zero-Overhead-Loop-Control" DSP-style Vector-style
+ Addition of two new "Zero-Overhead-Loop-Control" DSP-style Vector-style
Management Instructions which can be implemented extremely efficiently
and effectively by inserting an additional phase between Decode and Issue.
More complex designs are NOT adversely impacted and in fact greatly benefit
- whilst still retaining an obvious linear sequential execution programming model.
```
**Impact on software**:
**Keywords**:
```
- Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control,
- Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model
+ Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control (ZOLC),
+ Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
+ Digital Signal Processing (DSP)
```
**Motivation**
-TODO
+Power ISA is synonymous with Supercomputing and the early Supercomputers
+(ETA-10, ILLIAC-IV, CDC200, Cray) had Vectorisation. It is therefore anomalous
+that Power ISA does not have Scalable Vectors. This presents the opportunity to
+modernise Power ISA keeping it at the top of Supercomputing.
**Notes and Observations**:
-1. TODO
+1. SVP64 is very much designed for ultra-light-weight Embedded use-cases all the
+ way up to moving the bar of Supercomputing orders of magnitude above its present
+ perception, whilst retaining at all times Sequential Programming Execution.
+2. This proposal is the **base** for further Extensions. These include
+ extending SVP64 onto the Scalar VSX instructions (with a **LONG TERM** view in 10+ years
+ to deprecating the PackedSIMD aspects of VSX), to be discussed at a later
+ time, the potential for extending VSX registers to 128 or beyond, and Arithmetic
+ operations to a runtime-selectable choice of 128-bit, 256-bit, 512-bit or 1024-bit.
+3. Massive reductions in instruction count of between 2x and 20x have been demonstrated
+ with SVP64, which is far beyond anything ever achieved by any *general-purpose*
+ ISA Extension added to any ISA in the history of Computing.
**Changes**
Add the following entries to:
+* Section 1.3.2 Notation
* the Appendices of Book I
* Instructions of Book I as a new Section
* SVL-Form of Book I Section 1.6.1.6 and 1.6.2
\newpage{}
-# svstep: Vertical-First Stepping and status reporting
-
-SVL-Form
-
-* svstep RT,SVi,vf (Rc=0)
-* svstep. RT,SVi,vf (Rc=1)
-
-| 0-5|6-10|11.15|16..22| 23-25 | 26-30 |31| Form |
-|----|----|-----|------|----------|-------|--|--------- |
-|PO | RT | / | SVi | / / vf | XO |Rc| SVL-Form |
-
-Pseudo-code:
-
-```
- if SVi[3:4] = 0b11 then
- # store pack and unpack in SVSTATE
- SVSTATE[53] <- SVi[5]
- SVSTATE[54] <- SVi[6]
- RT <- [0]*62 || SVSTATE[53:54]
- else
- # Vertical-First explicit stepping.
- step <- SVSTATE_NEXT(SVi, vf)
- RT <- [0]*57 || step
-```
-
-Special Registers Altered:
+# Notation, Section 1.3.2
- CR0 (if Rc=1)
+When destination register operands (`RT, RS`) are prefixed by a single
+underscore (`_RT, _RS`) the variable also contains the contents of the
+instruction field.
+This avoids confusion in pseudocode when a destination register is
+assigned (`RT <- x`) but earlier it was the operand bits that were
+checked (`if RT = 0`)
--------------
+----------------
\newpage{}
-
-# setvl
-
-SVL-Form
-
-| 0-5|6-10|11-15|16-22 | 23 24 25 | 26-30 |31| FORM |
-| -- | -- | --- | ---- |----------| ----- |--|----------|
-|PO | RT | RA | SVi | ms vs vf | XO |Rc| SVL-Form |
-
-* setvl RT,RA,SVi,vf,vs,ms (Rc=0)
-* setvl. RT,RA,SVi,vf,vs,ms (Rc=1)
-
-Pseudo-code:
-
-```
- overflow <- 0b0 # sets CR.SO if set and if Rc=1
- VLimm <- SVi + 1
- # set or get MVL
- if ms = 1 then MVL <- VLimm[0:6]
- else MVL <- SVSTATE[0:6]
- # set or get VL
- if vs = 0 then VL <- SVSTATE[7:13]
- else if _RA != 0 then
- if (RA) >u 0b1111111 then
- VL <- 0b1111111
- overflow <- 0b1
- else VL <- (RA)[57:63]
- else if _RT = 0 then VL <- VLimm[0:6]
- else if CTR >u 0b1111111 then
- VL <- 0b1111111
- overflow <- 0b1
- else VL <- CTR[57:63]
- # limit VL to within MVL
- if VL >u MVL then
- overflow <- 0b1
- VL <- MVL
- SVSTATE[0:6] <- MVL
- SVSTATE[7:13] <- VL
- if _RT != 0 then
- GPR(_RT) <- [0]*57 || VL
- if ((¬vs) & ¬(ms)) = 0 then
- # set requested Vertical-First mode, clear persist
- SVSTATE[63] <- vf
- SVSTATE[62] <- 0b0
-```
-
-Special Registers Altered:
-
-```
- CR0 (if Rc=1)
-```
-
-* `SVi` - bits 16-22 - an immediate operand for setting MVL and/or VL
-* `ms` - bit 23 - allows for setting of MVL
-* `vs` - bit 24 - allows for setting of VL
-* `vf` - bit 25 - sets "Vertical First Mode".
-
-Note that in immediate setting mode VL and MVL start from **one**
-but that this is compensated for in the assembly notation.
-i.e. that an immediate value of 1 in assembler notation
-actually places the value 0b0000000 in the `SVi` field bits:
-on execution the `setvl` instruction adds one to the decoded
-`SVi` field bits, resulting in
-VL/MVL being set to 1. This allows VL to be set to values
-ranging from 1 to 128 with only 7 bits instead of 8.
-Setting VL/MVL
-to 0 would result in all Vector operations becoming `nop`. If this is
-truly desired (nop behaviour) then setting VL and MVL to zero is to be
-done via the [[SVSTATE SPR|sv/sprs]].
-
-Note that setmvli is a pseudo-op, based on RA/RT=0, and setvli likewise
-
- setvli VL=8 : setvl r0, r0, VL=8, vf=0, vs=1, ms=0
- setvli. VL=8 : setvl. r0, r0, VL=8, vf=0, vs=1, ms=0
- setmvli MVL=8 : setvl r0, r0, MVL=8, vf=0, vs=0, ms=1
- setmvli. MVL=8 : setvl. r0, r0, MVL=8, vf=0, vs=0, ms=1
-
-Additional pseudo-op for obtaining VL without modifying it (or any state):
-
- getvl r5 : setvl r5, r0, vf=0, vs=0, ms=0
- getvl. r5 : setvl. r5, r0, vf=0, vs=0, ms=0
-
--------------
-
-\newpage{}
+[[!inline pages="openpower/sv/svstep" raw=yes ]]
+[[!inline pages="openpower/sv/setvl" raw=yes ]]
# SVSTATE SPR
Field used in Simple-V to specify whether VL (vl in the SVSTATE SPR) is to be set
Formats: SVL
SVi (16:22)
- Simple-V immediate field for setting VL or MVL (vl, maxvl in the SVSTATE SPR)
+ Simple-V immediate field used by setvl for setting VL or MVL
+ (vl, maxvl in the SVSTATE SPR)
+ and used as a "Mode of Operation" selector in svstep
Formats: SVL
```
-
# Appendices
Appendix E Power ISA sorted by opcode
| Form | Book | Page | Version | mnemonic | Description |
|------|------|------|---------|----------|-------------|
| SVL | I | # | 3.0B | svstep | Vertical-First Stepping and status reporting |
+| SVL | I | # | 3.0B | setvl | Cray-like establishment of Looping (Vector) context |
+[[!tag opf_rfc]]
projects / libreriscv.git / blobdiff