# RFC ls011 LD/ST-Update-PostIncrement
-**URLs**:
-
+* Funded by NLnet under the Privacy and Enhanced Trust Programme, EU
+ Horizon2020 Grant 825310, and NGI0 Entrust No 101069594
* <https://bugs.libre-soc.org/show_bug.cgi?id=1048>
* <https://libre-soc.org/openpower/sv/rfc/ls011/>
* <https://bugs.libre-soc.org/show_bug.cgi?id=1045>
**Impact on processor**:
```
- TODO
+ Addition of new Load/Store Fixed and Floating Point instructions
```
**Impact on software**:
**Motivation**
-
+Moving the update of RA to *after* the Memory operation saves on instruction count
+both outside and inside hot-loops. strncpy may be reduced to 11 Vector instructions,
+3 of which are the zeroing loop, 5 of which are the copy. Percentage-wise LD/ST
+Update Post-Increment represents a massive 20% reduction.
**Notes and Observations**:
+These types of instructions are already present in x86 (sort-of).
+
+* x86 chose that store should be pre-indexed and load should be post-indexed
+* Power ISA chose everything to be pre-indexed
+* Motorola 68000 (decades old) has pre- and post- indexed
+
+<https://tack.sourceforge.net/olddocs/m68020.html#2.2.2.%20Extra%20MC68020%20addressing%20modes>
+<https://azeria-labs.com/memory-instructions-load-and-store-part-4/>
**Changes**
Add the following entries to:
-* A new "Vector Looping" Book
-* New Vector-Looping Chapters
-* New Vector-Looping Appendices
+* New Load/Store Sections
+* Appendices
[[!tag opf_rfc]]
-The following instructions are proposed to be added in EXT2xx,
-duplicating LD/ST-Update functionality but moving the update
-of RA to *after* the Memory operation. These types of
-instructions are already present in x86 (sort-of).
-
-* x86 chose that store should be pre-indexed and load should be post-indexed
-* Power ISA chose everything to be pre-indexed
-* Motorola 68000 (decades old) has pre- and post- indexed
-
-<https://tack.sourceforge.net/olddocs/m68020.html#2.2.2.%20Extra%20MC68020%20addressing%20modes>
-
-<https://azeria-labs.com/memory-instructions-load-and-store-part-4/>
-
The LD/ST-Immediate-Post-Increment instructions are all Primary
Opcode: there are 13 of these. LD/ST-Indexed-Post-Increment
are all effectively 9-bit XO and consequently may easily
stdupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
# FP LD/ST-Postincrement
-lfdu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
-lfsu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
-lfdux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
-lsdux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
-stfdu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
-stfsu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
-stfdux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
-stfsux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+lfdup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lfsup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lfdupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+lsdupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+stfdup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+stfsup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+stfdupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+stfsupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
# LD/ST-Shifted-Postincrement
-lbzuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
-lhzuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
-lhauspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
-lwzuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
-lwauspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
-lduspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
-stbuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
-sthuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
-stwuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
-stduspx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
+lbzupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
+lhzupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
+lhaupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
+lwzupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
+lwaupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
+ldupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
+stbupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
+sthupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
+stwupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
+stdupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
# FP LD/ST-Shifted-Postincrement
lfdupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
Add the following additional Section to Fixed-Point Load: Book I 3.3.2.1
-## Load Byte and Zero with Post-Update
-
-D-Form
-
-```
- |0 |6 |9 |10 |11 |16 |31 |
- | PO | RT | RA| D |
-```
-
-* lbzup RT,D(RA)
-
-Pseudo-code:
-
-```
- EA <- (RA)
- RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
- RA <- (RA) + EXTS(D)
-```
-
-Let the effective address (EA) be (RA|0).
-The byte in storage addressed by EA is loaded into
-RT[56:63]. RT[0:55] are set to 0.
-
-The sum (RA|0)+D is placed into register RA.
-
-If RA=0 or RA=RT, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
-## Load Byte and Zero with Post-Update Indexed
-
-X-Form
-
-```
- |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
- | PO | RT | RA | RB | XO | / |
-```
-
-* lbzupx RT,RA,RB
-
-Pseudo-code:
-
-```
- EA <- (RA)
- RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
- RA <- (RA) + (RB)
-```
-
-Let the effective address (EA) be (RA).
-The byte in storage addressed by EA is loaded into
-RT[56:63]. RT[0:55] are set to 0.
-
-The sum (RA)+(RB) is placed into register RA.
-
-If RA=0 or RA=RT, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
-## Load Halfword and Zero with Post-Update
-
-D-Form
-
-```
- |0 |6 |9 |10 |11 |16 |31 |
- | PO | RT | RA| D |
-```
-
-* lhzup RT,D(RA)
-
-Pseudo-code:
-
-```
- EA <- (RA)
- RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
- RA <- (RA) + EXTS(D)
-```
-
-Let the effective address (EA) be (RA|0).
-The halfword in storage addressed by EA is loaded into
-RT[48:63]. RT[0:47] are set to 0.
-
-The sum (RA|0)+D is placed into register RA.
-
-If RA=0 or RA=RT, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
-## Load Halfword and Zero with Post-Update Indexed
-
-X-Form
-
-```
- |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
- | PO | RT | RA | RB | XO | / |
-```
-
-* lhzupx RT,RA,RB
-
-Pseudo-code:
-
-```
- EA <- (RA)
- RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
- RA <- (RA) + (RB)
-```
-
-Let the effective address (EA) be (RA).
-The halfword in storage addressed by EA is loaded into
-RT[48:63]. RT[0:47] are set to 0.
-
-The sum (RA)+(RB) is placed into register RA.
-
-If RA=0 or RA=RT, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
-## Load Halfword Algebraic with Post-Update
-
-D-Form
-
-```
- |0 |6 |9 |10 |11 |16 |31 |
- | PO | RT | RA| D |
-```
-
-* lhaup RT,D(RA)
-
-Pseudo-code:
-
-```
- EA <- (RA)
- RT <- EXTS(MEM(EA, 2))
- RA <- (RA) + EXTS(D)
-```
-
-Special Registers Altered:
-
- None
-
-## Load Halfword Algebraic with Post-Update Indexed
-
-X-Form
-
-```
- |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
- | PO | RT | RA | RB | XO | / |
-```
-
-* lhaupx RT,RA,RB
-
-Pseudo-code:
-
-```
- EA <- (RA)
- RT <- EXTS(MEM(EA, 2))
- RA <- (RA) + (RB)
-```
-
-Special Registers Altered:
-
- None
-
-## Load Word and Zero with Post-Update
-
-D-Form
-
-```
- |0 |6 |9 |10 |11 |16 |31 |
- | PO | RT | RA| D |
-```
-
-* lwzup RT,D(RA)
-
-Pseudo-code:
-
-```
- EA <- (RA)
- RT <- [0]*32 || MEM(EA, 4)
- RA <- (RA) + EXTS(D)
-```
-
-Let the effective address (EA) be (RA|0).
-The word in storage addressed by EA is loaded into
-RT[32:63]. RT[0:31] are set to 0.
-
-The sum (RA|0)+D is placed into register RA.
-
-If RA=0 or RA=RT, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
-## Load Word and Zero with Post-Update Indexed
-
-X-Form
-
-```
- |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
- | PO | RT | RA | RB | XO | / |
-```
-
-* lwzupx RT,RA,RB
-
-Pseudo-code:
-
-```
- EA <- (RA)
- RT <- [0] * 32 || MEM(EA, 4)
- RA <- (RA) + (RB)
-```
-
-Let the effective address (EA) be (RA).
-The word in storage addressed by EA is loaded into
-RT[32:63]. RT[0:31] are set to 0.
-
-The sum (RA)+(RB) is placed into register RA.
-
-If RA=0 or RA=RT, the instruction form is invalid.
-
-Special Registers Altered:
-
- None
-
-## Load Word Algebraic with Post-Update Indexed
-
-X-Form
-
-```
- |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
- | PO | RT | RA | RB | XO | / |
-```
-
-* lwaupx RT,RA,RB
-
-Pseudo-code:
-
-```
- EA <- (RA)
- RT <- EXTS(MEM(EA, 4))
- RA <- (RA) + (RB)
-```
-
-Special Registers Altered:
-
- None
-
-## Load Doubleword with Post-Update Indexed
-
-DS-Form
-
-* ldup RT,DS(RA)
-
-Pseudo-code:
-
-```
- EA <- (RA)
- RT <- MEM(EA, 8)
- RA <- (RA) + EXTS(DS || 0b00)
-```
-
-Special Registers Altered:
-
- None
-
-## Load Doubleword with Post-Update Indexed
-
-X-Form
-
-```
- |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
- | PO | RT | RA | RB | XO | / |
-```
-
-* ldupx RT,RA,RB
-
-Pseudo-code:
-
-```
- EA <- (RA)
- RT <- MEM(EA, 8)
- RA <- (RA) + (RB)
-```
-
-Special Registers Altered:
-
- None
+[[!inline pages="openpower/isa/pifixedload" raw=yes ]]
-----
Add the following as a new section in Fixed-Point Store, Book I
-## Store Byte with Update
-
-D-Form
-
-```
- |0 |6 |9 |10 |11 |16 |31 |
- | PO | RT | RA| D |
-```
-
-* stbup RS,D(RA)
-
-Pseudo-code:
-
-```
- EA <- (RA) + EXTS(D)
- ea <- (RA)
- MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
- RA <- EA
-```
-
-Special Registers Altered:
-
- None
-
-## Store Byte with Update Indexed
-
-X-Form
-
-```
- |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
- | PO | RS | RA | RB | XO | / |
-```
-
-* stbupx RS,RA,RB
-
-Pseudo-code:
-
-```
- EA <- (RA) + (RB)
- ea <- (RA)
- MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
- RA <- EA
-```
-
-Special Registers Altered:
-
- None
-
-## Store Halfword with Update
+[[!inline pages="openpower/isa/pifixedstore" raw=yes ]]
-D-Form
-
-```
- |0 |6 |9 |10 |11 |16 |31 |
- | PO | RT | RA| D |
-```
-
-* sthup RS,D(RA)
-
-Pseudo-code:
-
-```
- EA <- (RA) + EXTS(D)
- ea <- (RA)
- MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
- RA <- EA
-```
-
-Special Registers Altered:
-
- None
-
-## Store Halfword with Update Indexed
-
-X-Form
-
-```
- |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
- | PO | RS | RA | RB | XO | / |
-```
-
-* sthupx RS,RA,RB
-
-Pseudo-code:
-
-```
- EA <- (RA) + (RB)
- ea <- (RA)
- MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
- RA <- EA
-```
-
-Special Registers Altered:
-
- None
-
-## Store Word with Update
-
-D-Form
-
-```
- |0 |6 |9 |10 |11 |16 |31 |
- | PO | RT | RA| D |
-```
-
-* stwup RS,D(RA)
-
-Pseudo-code:
-
-```
- EA <- (RA) + EXTS(D)
- ea <- (RA)
- MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
- RA <- EA
-```
-
-Special Registers Altered:
-
- None
-
-## Store Word with Update Indexed
-
-X-Form
-
-```
- |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
- | PO | RS | RA | RB | XO | / |
-```
+-----
-* stwupx RS,RA,RB
+\newpage{}
-Pseudo-code:
+# Floating-Point Load Post-Update
-```
- EA <- (RA) + (RB)
- ea <- (RA)
- MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
- RA <- EA
-```
+Add the following as a new section in Floating-Point Load, Book I 4.6.2
-Special Registers Altered:
+[[!inline pages="openpower/isa/fpload" raw=yes ]]
- None
+-----
-## Store Doubleword with Update
+\newpage{}
-DS-Form
+# Floating-Point Store Post-Update
-* stdup RS,DS(RA)
+Add the following as a new section in Floating-Point Store, Book I 4.6.3
-Pseudo-code:
+[[!inline pages="openpower/isa/fpstore" raw=yes ]]
-```
- EA <- (RA) + EXTS(DS || 0b00)
- ea <- (RA)
- MEM(ea, 8) <- (RS)
- RA <- EA
-```
+-----
-Special Registers Altered:
+\newpage{}
- None
+# Fixed-Point Load Shifted Post-Update
-## Store Doubleword with Update Indexed
+Add the following as a new section in Fixed-Point Load: Book I
-X-Form
+[[!inline pages="openpower/isa/pifixedloadshift" raw=yes ]]
-```
- |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
- | PO | RS | RA | RB | XO | / |
-```
+-----
-* stdupx RS,RA,RB
+\newpage{}
-Pseudo-code:
+# Fixed-Point Store Shifted Post-Update
-```
- EA <- (RA) + (RB)
- ea <- (RA)
- MEM(ea, 8) <- (RS)
- RA <- EA
-```
+Add the following as a new section in Fixed-Point Store: Book I
-Special Registers Altered:
+[[!inline pages="openpower/isa/pifixedstoreshift" raw=yes ]]
- None
+\newpage{}
+[[!inline pages="openpower/isa/fixedload" raw=yes ]]
+\newpage{}
+[[!inline pages="openpower/isa/fixedstore" raw=yes ]]
[[!tag opf_rfc]]
projects / libreriscv.git / blobdiff