add postinc reg profiles to optables.csv

[libreriscv.git] / openpower / sv / rfc / ls012.mdwn

diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 68a57e2c8eab25f19c6fe33f9ca92df1f7c6a3a4..0bbfa2abd2d840bfcc8058dc9b7d22b4319efd65 100644 (file)
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -370,7 +370,8 @@ The key to headings and sections are as follows:
 * **XO Cost** - the number of bits required in the XO Field. whilst not
   the full picture it is a good indicator as to how costly in terms
   of Opcode Allocation a given instruction will be.  Lower number is
-  a higher cost for the Power ISA's precious remaining Opcode space
+  a higher cost for the Power ISA's precious remaining Opcode space.
+  "PO" indicates that an entire Primary Opcode is required.
 * **rfc** the Libre-SOC External RFC resource,
   <https://libre-soc.org/openpower/sv/rfc/> where advance notice of
   upcoming RFCs in development may be found.
@@ -389,6 +390,12 @@ The key to headings and sections are as follows:
   (UnVectoriseable),
   EXT3xx, was available in an early Draft RFC but has been made "RESERVED"
   instead.  see [[sv/po9_encoding]].
+* **regs** - a guide to register usage, to how costly Hazard Management
+  will be, in hardware:
+  - 1R: reads one GPR/FPR/SPR/CR.
+  - 1W: writes one GPR/FPR/SPR/CR. 
+  - 1r: reads one CR *Field*.
+  - 1w: writes one CR *Field*
 
 [[!inline pages="openpower/sv/rfc/ls012/areas.mdwn" raw=yes ]]
 [[!inline pages="openpower/sv/rfc/ls012/xo_cost.mdwn" raw=yes ]]