whoops heading1 not heading2

[libreriscv.git] / openpower / sv / rfc / ls012.mdwn

diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 77df724924ac5730a840e6e1c17662c9d811b11e..475d4b3b2decf0d003e1b146b07f27259f4e1bd3 100644 (file)
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -316,7 +316,7 @@ introduce mv Swizzle operations, which can always be Macro-op fused
 in exactly the same way that ARM SVE predicated-move extends 3-operand
 "overwrite" opcodes to full independent 3-in 1-out.
 
-# BMI (bitmanipulation) group.
+## BMI (bitmanipulation) group.
 
 Whilst the [[sv/vector_ops]] instructions are only two in number, in
 reality the `bmask` instruction has a Mode field allowing it to cover