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[libreriscv.git] / openpower / sv / rfc / ls012.mdwn

diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 57461df9cda3a6087112a8a59e629b9aacb17cb9..9ee2012f22c738dd247c0bf655e25a619aa0c5c1 100644 (file)
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -240,8 +240,9 @@ as just one example.
 These LUT2/3 operations are high cost high reward. Outlined in
 [[sv/bitmanip]], the simplest ones already exist in PackedSIMD VSX:
 `xxeval`.  The same reasoning applies as to fclass: SFFS needs to be
-stand-alone on its own merits and not "punished" should an implementor
-choose not to implement any aspect of PackedSIMD VSX.
+stand-alone on its own merits and should an implementor
+choose not to implement any aspect of PackedSIMD VSX the performance
+of their product should not be penalised for making that decision.
 
 With Predication being such a high priority in GPUs and HPC, CR Field
 variants of Ternary and Binary LUT instructions were considered high