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[libreriscv.git] / openpower / sv / setvl.mdwn

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 50939b6b542432303dccb9e426f4e541b749e408..f0ea713ae30a4e036fdbe0889cad67ea6185441d 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -128,10 +128,10 @@ from different sources is as follows:
 
 | condition           | effect         |
 | - | - |
-| `vf=1, RA=0, RT!=0` | VL,RT set to MIN(MVL, CTR)  |
-| `vf=1, RA=0, RT=0`  | VL set to MIN(MVL, SVi+1)  |
-| `vf=1, RA!=0, RT=0` | VL set to MIN(MVL, RA)  |
-| `vf=1, RA!=0, RT!=0` | VL,RT set to MIN(MVL, RA)  |
+| `vs=1, RA=0, RT!=0` | VL,RT set to MIN(MVL, CTR)  |
+| `vs=1, RA=0, RT=0`  | VL set to MIN(MVL, SVi+1)  |
+| `vs=1, RA!=0, RT=0` | VL set to MIN(MVL, RA)  |
+| `vs=1, RA!=0, RT!=0` | VL,RT set to MIN(MVL, RA)  |
 
 The reasoning here is that the opportunity to set RT equal to the
 immediate `SVi+1` is sacrificed in favour of setting from CTR.