re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / openpower / sv / setvl.mdwn

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index d6cb15dc0fbdbe3addd5016a79a170a2b151da6f..f5e66c42a58547a9afa932bb162a28841f519747 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -89,7 +89,11 @@ Instruction format:
     setvl RT,RA,SVi,vf,vs,ms
     setvl. RT,RA,SVi,vf,vs,ms
 
-Note that the immediate (`SVi`) spans 7 bits (16 to 22)
+Note that the immediate (`SVi`) spans 7 bits (16 to 22).
+
+Instruction encodings where `SVi`'s MSB is set are reserved for future extensions.
+Implementations are required to cause an illegal instruction exception when
+`SVi`'s MSB is set to allow software emulation of those future extensions.
 
 * `ms` - bit 23 - allows for setting of MVL
 * `vs` - bit 24 - allows for setting of VL