update

[libreriscv.git] / pinmux / pinmux_chennai_2018.tex

diff --git a/pinmux/pinmux_chennai_2018.tex b/pinmux/pinmux_chennai_2018.tex
index b3578ee3b5f9c826e9cfb9b80dc42e7ecb4c85cb..0901b67fb283177c88466505302a3f71e10d1225 100644 (file)
--- a/pinmux/pinmux_chennai_2018.tex
+++ b/pinmux/pinmux_chennai_2018.tex
@@ -141,7 +141,7 @@
 \frame{\frametitle{Associated Extras}
 
  \begin{itemize}
-   \item Design Specification (what markets to target)
+   \item Design Specification ({\bf what} markets to target)
    \item Scenario analysis ({\bf whether} the chip will fit "markets")
    \item Documentation: Summary sheet, Technical Reference Manual.
    \item Test suites
@@ -190,21 +190,23 @@
 \frame{\frametitle{Reduce workload, reduce duplication, reduce risk and cost}
 
  \begin{itemize}
-   \item Auto-generate everything: documentation, code, libraries etc.
-            \vspace{10pt}
+   \item Auto-generate everything: documentation, code, libraries etc.\\
+            (including device-tree files, FreeBSD / Linux / RTOS kernel
+            drivers, Arduino, libopencm3 and other EC firmware libraries)
+            \vspace{4pt}
    \item Standardise: similar to PLIC, propose GPIO and Pinmux\\
             saves engineering effort, design effort and much more
-            \vspace{10pt}
+            \vspace{4pt}
    \item Standardise format of configuration registers:
             saves code duplication effort (multiple software environments)
-                \vspace{10pt}
+                \vspace{4pt}
    \item Add support for multiple code formats: Chisel3 (SiFive IOF),
             BSV (Bluespec), Verilog, VHDL, MyHDL.
-                \vspace{10pt}
+                \vspace{4pt}
    \item Multiple auto-generated code-formats permits cross-validation:\\
             auto-generated test suite in one HDL can validate a muxer
             generated for a different target HDL.
-                \vspace{10pt}
+                \vspace{4pt}
   \end{itemize}
 }