re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / resources.mdwn

diff --git a/resources.mdwn b/resources.mdwn
index 3d9a4a93fe82c03516c9a125ec42adccdcaa903d..8f0a856420db2000a689272536b233a3abd9347a 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -349,10 +349,6 @@ Some learning resources I found in the community:
 # Python RTL Tools
 
 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
-* [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
-  An SOC builder written in Python Migen DSL. Allows you to generate functional
-  RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
-  and parameterizeable CSRs.
 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
 * There is a great guy, Robert Baruch, who has a good
   [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
@@ -402,7 +398,8 @@ Some learning resources I found in the community:
 * Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
-<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf> 
+<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
+* adrian_b architecture comparison <https://news.ycombinator.com/item?id=24459041>
 
 # Real/Physical Projects
 
@@ -535,5 +532,6 @@ This list auto-generated from a page tag "standards":
      LowRISC is UK based
      https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
     https://cirosantilli.com/x86-paging
+    https://stackoverflow.com/questions/18431261/how-does-x86-paging-work
     http://denninginstitute.com/modules/vm/red/i486page.html
 ```