re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / resources.mdwn

diff --git a/resources.mdwn b/resources.mdwn
index f7a1e0ea31fa6ed974edf28b73283c9fc41e1d68..8f0a856420db2000a689272536b233a3abd9347a 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -23,7 +23,8 @@ This section is primarily a series of useful links found online
 
 ## Overview of the user ISA:
 
-[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* Power ISA listings <https://power-isa-beta.mybluemix.net/>
 
 ## OpenPOWER OpenFSI Spec (2016)
 
@@ -31,12 +32,26 @@ This section is primarily a series of useful links found online
 
 * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
 
+# Energy-efficient cores
+
+* https://arxiv.org/abs/2002.10143
+
 # Communities
 
 * <https://www.reddit.com/r/OpenPOWER/>
 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
+* Open tape-out mailing list <https://groups.google.com/a/opentapeout.dev/g/mailinglist>
+
+# Other GPU Specifications
 
+* 
+* https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf 
+* https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf 
+* MALI Midgard
+* [Nyuzi](https://github.com/jbush001/NyuziProcessor)
+* VideoCore IV
+* etnaviv
 
 # JTAG
 
@@ -51,8 +66,13 @@ This section is primarily a series of useful links found online
 
 # D-Cache
 
+- [A Primer on Memory Consistency and Cache Coherence
+](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049)
+
 ## D-Cache Possible Optimizations papers and links
 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
+- [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
+Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901)
 
 # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
 - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
@@ -201,6 +221,11 @@ see [[conferences]]
 Note: The rest of LIP6's website is in French, but there is a UK flag
 in the corner that gives the English version.
 
+# Logical Equivalence and extraction
+
+* NETGEN
+* CVC https://github.com/d-m-bailey/cvc
+
 # Klayout
 
 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
@@ -282,6 +307,8 @@ thousands or millions of silicon.
 * Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
 
 * Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
+* Minisail <https://www.isa-afp.org/entries/MiniSail.html> - compiler
+  for SAIL into c
 
 Some learning resources I found in the community:
 
@@ -297,6 +324,18 @@ Some learning resources I found in the community:
 
 * <https://www.ohwr.org/project/wishbone-gen>
 
+# Bus Architectures
+
+* Avalon <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf>
+* CXM <https://www.computeexpresslink.org/download-the-specification>
+
+# Vector Processors
+
+* THOR <https://github.com/robfinch/Thor/blob/main/Thor2021/doc/Thor2021.pdf>
+* NEC SX-Aurora
+* RVV
+* MRISC32 <https://github.com/mrisc32/mrisc32>
+
 # LLVM
 
 ## Adding new instructions:
@@ -310,10 +349,6 @@ Some learning resources I found in the community:
 # Python RTL Tools
 
 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
-* [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
-  An SOC builder written in Python Migen DSL. Allows you to generate functional
-  RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
-  and parameterizeable CSRs.
 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
 * There is a great guy, Robert Baruch, who has a good
   [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
@@ -321,16 +356,13 @@ Some learning resources I found in the community:
   [the code](https://github.com/RobertBaruch/n6800) and
   [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
   online.
-* [Minerva](https://github.com/lambdaconcept/minerva)
-  An SOC written in Python nMigen DSL
-* Minerva example using nmigen-soc
-  <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
+  There is now a page [[docs/learning_nmigen]].
 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
-* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
 
 # Other
 
+* <https://github.com/tdene/synth_opt_adders> Prefix-tree generation scripts
 * <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
 * <https://codeberg.org/tok/librecell> Libre Cell Library
 * <https://wiki.f-si.org/index.php/FSiC2019>
@@ -338,6 +370,8 @@ Some learning resources I found in the community:
 * <https://www.lowrisc.org/open-silicon/>
 * <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
 * <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
+* <https://github.com/Ben1152000/sootty> - console-based vcd viewer
+* <https://github.com/ics-jku/wal> - Waveform Analysis
 * <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
   Synchronous Resets? Asynchronous Resets? I am so confused! How will I
   ever know which to use? by Clifford E. Cummings
@@ -350,7 +384,7 @@ Some learning resources I found in the community:
   Understanding Latency Hiding on GPUs, by Vasily Volkov
 * Efabless "Openlane" <https://github.com/efabless/openlane>
 * example of openlane with nmigen
-  <https://gist.github.com/lethalbit/e65e296bc6a3810280d1b256c9df591b>
+  <https://github.com/lethalbit/nmigen/tree/openlane>
 * Co-simulation plugin for verilator, transferring to ECP5
   <https://github.com/vmware/cascade>
 * Multi-read/write ported memories
@@ -364,7 +398,9 @@ Some learning resources I found in the community:
 * Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
-<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf> 
+<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
+* adrian_b architecture comparison <https://news.ycombinator.com/item?id=24459041>
+
 # Real/Physical Projects
 
 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
@@ -495,4 +531,7 @@ This list auto-generated from a page tag "standards":
      OpenTitan also uses FuseSoC
      LowRISC is UK based
      https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
+    https://cirosantilli.com/x86-paging
+    https://stackoverflow.com/questions/18431261/how-does-x86-paging-work
+    http://denninginstitute.com/modules/vm/red/i486page.html
 ```