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[libreriscv.git] / resources.mdwn
diff --git a/resources.mdwn b/resources.mdwn
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@@ -20,6 +20,9 @@ This section is primarily a series of useful links found online
 
 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
+* Virginia Tech course <https://github.com/w-feng/CompArch-MIPS-POWER>
+* mini functional simulator https://github.com/god-s-perfect-idiot/POWER-sim
+* https://raw.githubusercontent.com/linuxppc/public-docs/main/ISA/PowerPC_Assembly_IBM_Programming_Environment_2.3.pdf
 
 ## Overview of the user ISA:
 
@@ -35,6 +38,11 @@ This section is primarily a series of useful links found online
 # Energy-efficient cores
 
 * https://arxiv.org/abs/2002.10143
+* https://arxiv.org/abs/2011.08070
+
+# Open Access Publication locations
+
+* <https://open-research-europe.ec.europa.eu/browse/engineering-and-technology>
 
 # Communities
 
@@ -43,6 +51,17 @@ This section is primarily a series of useful links found online
 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
 * Open tape-out mailing list <https://groups.google.com/a/opentapeout.dev/g/mailinglist>
 
+# ppc64 ELF ABI
+
+* EABI 1.9 supplement <https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.html>
+* https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.pdf
+* v2.1.5 <https://openpowerfoundation.org/specifications/64bitelfabi/>
+
+# Similar concepts
+
+* <https://www.tdx.cat/bitstream/handle/10803/674224/TCRL1de1.pdf> Vector registers may be
+  made "ultra-wide" (SX Aurora / Cray)
+
 # Other GPU Specifications
 
 * 
@@ -53,6 +72,21 @@ This section is primarily a series of useful links found online
 * VideoCore IV
 * etnaviv
 
+# Other CPUs and ISAs worth considering
+
+* https://en.m.wikipedia.org/wiki/Zilog_Z380
+* Mitch Alsup 66000
+* Hitachi Sh2
+  https://lists.j-core.org/pipermail/j-core/
+  http://shared-ptr.com/sh_insns.html
+* 68080 except Length-Decode is a pig for Multi-Issue
+  http://www.apollo-core.com/index.htm?page=coding&tl=1
+
+# Package Management
+
+* <https://packages.debian.org/search?keywords=proot>
+* <https://github.com/stb-tester/apt2ostree>
+
 # JTAG
 
 * [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf)
@@ -320,6 +354,15 @@ Some learning resources I found in the community:
 * <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
 * <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
 
+VAMP CPU
+
+* Formal verification of a fully IEEE compliant floating point unit
+<https://publikationen.sulb.uni-saarland.de/bitstream/20.500.11880/25760/1/ChristianJacobi_ProfDrWolfgangJPaul.pdf>
+* <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/?lang=en>
+* the PVS/hw subfolder is under the 2-clause BSD license:
+    <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/PVS/hw/COPYRIGHT>
+* <https://alastairreid.github.io/RelatedWork/papers/beyer:ijsttt:2006/>
+
 ## Automation
 
 * <https://www.ohwr.org/project/wishbone-gen>
@@ -348,11 +391,9 @@ Some learning resources I found in the community:
 
 # Python RTL Tools
 
+* <https://ieeexplore.ieee.org/document/9591456> pylog fpga
+  <https://github.com/hst10/pylog>
 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
-* [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
-  An SOC builder written in Python Migen DSL. Allows you to generate functional
-  RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
-  and parameterizeable CSRs.
 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
 * There is a great guy, Robert Baruch, who has a good
   [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
@@ -366,6 +407,11 @@ Some learning resources I found in the community:
 
 # Other
 
+* <https://github.com/chrische-xx/mpw7> 10-bit SAR ADC
+* Cray-1 Pocket Reference
+  <https://nitter.it/aka_pugs/status/1546576975166201856>
+  <https://ftp.libre-soc.org/cray-1-pocket-ref/>
+  <https://www.computerhistory.org/collections/catalog/102685876>
 * <https://github.com/tdene/synth_opt_adders> Prefix-tree generation scripts
 * <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
 * <https://codeberg.org/tok/librecell> Libre Cell Library
@@ -402,7 +448,9 @@ Some learning resources I found in the community:
 * Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
-<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf> 
+<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
+* adrian_b architecture comparison <https://news.ycombinator.com/item?id=24459041>
+* ericandecscent RISC-V <https://libre-soc.org/irclog/%23libre-soc.2021-07-11.log.html>
 
 # Real/Physical Projects
 
@@ -429,7 +477,7 @@ Some learning resources I found in the community:
 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
-* [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
+* [It's not a zero-sum game](https://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
 
 * <https://youtu.be/o5Ihqg72T3c>
 * <http://flopoco.gforge.inria.fr/>
@@ -510,9 +558,20 @@ This list auto-generated from a page tag "standards":
 * <https://arxiv.org/pdf/1501.06511.pdf>
 * <https://bivector.net/index.html>
 
+# Handy Compiler Algorithms for SimpleV
+
+Requires aligned registers:
+
+* [Graph Coloring Register Allocation for Processors with Multi-Register Operands](https://dl.acm.org/doi/pdf/10.1145/93548.93552)
+
+More general:
+
+* [Retargetable Graph-Coloring Register Allocation for Irregular Architectures](https://user.it.uu.se/~svenolof/wpo/AllocSCOPES2003.20030626b.pdf)
+
 # TODO investigate
 
 ```
+     https://www.nextplatform.com/2022/08/22/the-expanding-cxl-memory-hierarchy-is-inevitable-and-good-enough/
      https://github.com/idea-fasoc/OpenFASOC
      https://www.quicklogic.com/2020/06/18/the-tipping-point/
      https://www.quicklogic.com/blog/
@@ -535,5 +594,7 @@ This list auto-generated from a page tag "standards":
      LowRISC is UK based
      https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
     https://cirosantilli.com/x86-paging
+    https://stackoverflow.com/questions/18431261/how-does-x86-paging-work
     http://denninginstitute.com/modules/vm/red/i486page.html
+    https://m.slashdot.org/story/391021 - mirror neural atrophy results in destruction of empathy
 ```
http://libre-riscv.org ikiwiki