* [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
* [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
+* Virginia Tech course <https://github.com/w-feng/CompArch-MIPS-POWER>
+* mini functional simulator https://github.com/god-s-perfect-idiot/POWER-sim
+* https://raw.githubusercontent.com/linuxppc/public-docs/main/ISA/PowerPC_Assembly_IBM_Programming_Environment_2.3.pdf
## Overview of the user ISA:
-[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* Power ISA listings <https://power-isa-beta.mybluemix.net/>
## OpenPOWER OpenFSI Spec (2016)
* [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
-## JTAG
+# Energy-efficient cores
-* [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://airccj.org/CSCP/vol6/csit65610.pdf)
+* https://arxiv.org/abs/2002.10143
+* https://arxiv.org/abs/2011.08070
- Abstract
+# Open Access Publication locations
- "The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications."
+* <https://open-research-europe.ec.europa.eu/browse/engineering-and-technology>
+
+# Communities
+
+* <https://www.reddit.com/r/OpenPOWER/>
+* <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
+* <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
+* Open tape-out mailing list <https://groups.google.com/a/opentapeout.dev/g/mailinglist>
+
+# ppc64 ELF ABI
+
+* EABI 1.9 supplement <https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.html>
+* https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.pdf
+* v2.1.5 <https://openpowerfoundation.org/specifications/64bitelfabi/>
+
+# Similar concepts
+
+* <https://www.tdx.cat/bitstream/handle/10803/674224/TCRL1de1.pdf> Vector registers may be
+ made "ultra-wide" (SX Aurora / Cray)
+
+# Other GPU Specifications
-# RISC-V Instruction Set Architecture
+*
+* https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf
+* https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf
+* MALI Midgard
+* [Nyuzi](https://github.com/jbush001/NyuziProcessor)
+* VideoCore IV
+* etnaviv
-**PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
-RISCV
+# Other CPUs and ISAs worth considering
-The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
-of the project implies, we will be following the RISC-V ISA I due to it
-being open-source and also because of the huge software and hardware
-ecosystem building around it. There are other open-source ISAs but none
-of them have the same momentum and energy behind it as RISC-V.
+* https://en.m.wikipedia.org/wiki/Zilog_Z380
+* Mitch Alsup 66000
+* Hitachi Sh2
+ https://lists.j-core.org/pipermail/j-core/
+ http://shared-ptr.com/sh_insns.html
+* 68080 except Length-Decode is a pig for Multi-Issue
+ http://www.apollo-core.com/index.htm?page=coding&tl=1
-To fully take advantage of the RISC-V ecosystem, it is important to be
-compliant with the RISC-V standards. Doing so will allow us to to reuse
-most software as-is and avoid major forks.
+# Package Management
-* [Official compiled PDFs of RISC-V ISA Manual]
- (https://github.com/riscv/riscv-isa-manual/releases/latest)
-* [Working draft of the proposed RISC-V Bitmanipulation extension](https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf)
-* [RISC-V "V" Vector Extension](https://riscv.github.io/documents/riscv-v-spec/)
-* [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
+* <https://packages.debian.org/search?keywords=proot>
+* <https://github.com/stb-tester/apt2ostree>
-Note: As far as I know, we aren't using the RISC-V V Extension directly
-at the moment. However, there are many wiki pages that make a reference
-to the V extension so it would be good to include it here as a reference
-for comparative/informative purposes with regard to Simple-V.
+# JTAG
+
+* [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf)
+
+ Abstract
+
+ "The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications."
# Radix MMU
- [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
# D-Cache
+- [A Primer on Memory Consistency and Cache Coherence
+](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049)
+
## D-Cache Possible Optimizations papers and links
- [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
+- [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
+Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901)
# BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
- [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
# RTL Arithmetic SQRT, FPU etc.
+## Wallace vs Dadda Multipliers
+
+* [Paper comparing efficiency of Wallace and Dadda Multipliers in RTL implementations (clicking will download the pdf from archive.org)](https://web.archive.org/web/20180717013227/http://ieeemilestones.ethw.org/images/d/db/A_comparison_of_Dadda_and_Wallace_multiplier_delays.pdf)
+
## Sqrt
* [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
* [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
+* [Fast Calculation of Cube and Inverse Cube Roots Using a Magic Constant and Its Implementation on Microcontrollers (clicking will download the pdf)](https://res.mdpi.com/d_attachment/energies/energies-14-01058/article_deploy/energies-14-01058-v2.pdf)
+* [Modified Fast Inverse Square Root and Square Root Approximation Algorithms: The Method of Switching Magic Constants (clicking will download the pdf)](https://res.mdpi.com/d_attachment/computation/computation-09-00021/article_deploy/computation-09-00021-v3.pdf)
+
## CORDIC and related algorithms
* [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
* [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
* <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
+* <https://dspguru.com/dsp/faqs/cordic/>
## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
Note: Even though this is such an important standard used by everyone,
it is unfortunately not freely available and requires a payment to
-access. However, each of the Libre RISC-V members already have access
+access. However, each of the Libre-SOC members already have access
to the document.
* [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
* [Intel Underestimates Error Bounds by 1.3 quintillion on
Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
* [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
+* How not to design an ISA
+ <https://player.vimeo.com/video/450406346>
+ Meester Forsyth <http://eelpi.gotdns.org/>
# Khronos Standards
OpenCL while relying on other software projects to translate APIs to
Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
+# Open Source (CC BY + MIT) DirectX specs (by Microsoft, but not official specs)
+
+https://github.com/Microsoft/DirectX-Specs
+
# Graphics and Compute API Stack
I found this informative post that mentions Kazan and a whole bunch of
* [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
+# 3D Graphics Texture compression software and hardware
+
+* [Proprietary Rad Game Tools Oddle Texture Software Compression](https://web.archive.org/web/20200913122043/http://www.radgametools.com/oodle.htm)
+
+* [Blog post by one of the engineers who developed the proprietary Rad Game Tools Oddle Texture Software Compression and the Oodle Kraken decompression software and hardware decoder used in the ps5 ssd](https://archive.vn/oz0pG)
# Various POWER Communities
- [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
# Conferences
-## Free Silicon Conference
+see [[conferences]]
-The conference brought together experts and enthusiasts who want to build
-a complete Free and Open Source CAD ecosystem for designing analog and
-digital integrated circuits. The conference covered the full spectrum of
-the design process, from system architecture, to layout and verification.
-* <https://wiki.f-si.org/index.php/FSiC2019#Foundries.2C_PDKs_and_cell_libraries>
+# Coriolis2
* LIP6's Coriolis - a set of backend design tools:
<https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
Note: The rest of LIP6's website is in French, but there is a UK flag
in the corner that gives the English version.
+# Logical Equivalence and extraction
+
+* NETGEN
+* CVC https://github.com/d-m-bailey/cvc
+
+# Klayout
+
* KLayout - Layout viewer and editor: <https://www.klayout.de/>
+# image to GDS-II
+
+* https://nazca-design.org/convert-image-to-gds/
+
# The OpenROAD Project
OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
verification as a final step in the development process before we produce
thousands or millions of silicon.
+* Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
+
+* Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
+* Minisail <https://www.isa-afp.org/entries/MiniSail.html> - compiler
+ for SAIL into c
+
Some learning resources I found in the community:
* ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
* <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
* <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
+VAMP CPU
+
+* Formal verification of a fully IEEE compliant floating point unit
+<https://publikationen.sulb.uni-saarland.de/bitstream/20.500.11880/25760/1/ChristianJacobi_ProfDrWolfgangJPaul.pdf>
+* <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/?lang=en>
+* the PVS/hw subfolder is under the 2-clause BSD license:
+ <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/PVS/hw/COPYRIGHT>
+* <https://alastairreid.github.io/RelatedWork/papers/beyer:ijsttt:2006/>
+
## Automation
* <https://www.ohwr.org/project/wishbone-gen>
+# Bus Architectures
+
+* Avalon <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf>
+* CXM <https://www.computeexpresslink.org/download-the-specification>
+
+# Vector Processors
+
+* THOR <https://github.com/robfinch/Thor/blob/main/Thor2021/doc/Thor2021.pdf>
+* NEC SX-Aurora
+* RVV
+* MRISC32 <https://github.com/mrisc32/mrisc32>
+
# LLVM
## Adding new instructions:
# Python RTL Tools
+* <https://ieeexplore.ieee.org/document/9591456> pylog fpga
+ <https://github.com/hst10/pylog>
* [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
-* [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
- An SOC builder written in Python Migen DSL. Allows you to generate functional
- RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
- and parameterizeable CSRs.
* [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
* There is a great guy, Robert Baruch, who has a good
[tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
[the code](https://github.com/RobertBaruch/n6800) and
[instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
online.
-* [Minerva](https://github.com/lambdaconcept/minerva)
- An SOC written in Python nMigen DSL
+ There is now a page [[docs/learning_nmigen]].
* [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
* <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
-* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
# Other
+* <https://github.com/chrische-xx/mpw7> 10-bit SAR ADC
+* Cray-1 Pocket Reference
+ <https://nitter.it/aka_pugs/status/1546576975166201856>
+ <https://ftp.libre-soc.org/cray-1-pocket-ref/>
+ <https://www.computerhistory.org/collections/catalog/102685876>
+* <https://github.com/tdene/synth_opt_adders> Prefix-tree generation scripts
+* <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
+* <https://codeberg.org/tok/librecell> Libre Cell Library
* <https://wiki.f-si.org/index.php/FSiC2019>
* <https://fusesoc.net>
* <https://www.lowrisc.org/open-silicon/>
* <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
* <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
+* <https://github.com/Ben1152000/sootty> - console-based vcd viewer
+* <https://github.com/ics-jku/wal> - Waveform Analysis
* <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
Synchronous Resets? Asynchronous Resets? I am so confused! How will I
ever know which to use? by Clifford E. Cummings
* <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
Understanding Latency Hiding on GPUs, by Vasily Volkov
* Efabless "Openlane" <https://github.com/efabless/openlane>
+* example of openlane with nmigen
+ <https://github.com/lethalbit/nmigen/tree/openlane>
* Co-simulation plugin for verilator, transferring to ECP5
<https://github.com/vmware/cascade>
* Multi-read/write ported memories
<https://arxiv.org/pdf/1803.06185.pdf>
* OpenPOWER Foundation Membership
<https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
-
+* Clock switching (and formal verification)
+ <https://zipcpu.com/formal/2018/05/31/clkswitch.html>
+* Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
+* Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
+* Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
+<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
+* adrian_b architecture comparison <https://news.ycombinator.com/item?id=24459041>
+* ericandecscent RISC-V <https://libre-soc.org/irclog/%23libre-soc.2021-07-11.log.html>
# Real/Physical Projects
* [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
* [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
* <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
-* [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
+* [It's not a zero-sum game](https://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
* <https://youtu.be/o5Ihqg72T3c>
* <http://flopoco.gforge.inria.fr/>
# CircuitJS experiments
* [[resources/high-speed-serdes-in-circuitjs]]
+
+# Logic Simulator 2
+* <https://github.com/dkilfoyle/logic2>
+[Live web version](https://dkilfoyle.github.io/logic2/)
+
+> ## Features
+> 1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr)
+> 2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints
+> 3. IDE docking ui courtesy of JupyterLab's Lumino widgets
+> 4. Schematic visualisation courtesy of d3-hwschematic
+> 5. Testbench simulation with graphical trace output and schematic animation
+> 6. Circuit description as gates, boolean logic or verilog behavioural model
+> 7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map
+
+[from the GitHub page. As of 2021/03/29]
+
+# ASIC Timing and Design flow resources
+
+* <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
+* <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
+* <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
+* <https://en.wikipedia.org/wiki/Frequency_divider>
+
+# Geometric Haskell Library
+
+* <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/GeometricAlgebra.hs>
+* <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/PGA.hs>
+* <https://arxiv.org/pdf/1501.06511.pdf>
+* <https://bivector.net/index.html>
+
+# Handy Compiler Algorithms for SimpleV
+
+Requires aligned registers:
+
+* [Graph Coloring Register Allocation for Processors with Multi-Register Operands](https://dl.acm.org/doi/pdf/10.1145/93548.93552)
+
+More general:
+
+* [Retargetable Graph-Coloring Register Allocation for Irregular Architectures](https://user.it.uu.se/~svenolof/wpo/AllocSCOPES2003.20030626b.pdf)
+
+# TODO investigate
+
+```
+ https://www.nextplatform.com/2022/08/22/the-expanding-cxl-memory-hierarchy-is-inevitable-and-good-enough/
+ https://github.com/idea-fasoc/OpenFASOC
+ https://www.quicklogic.com/2020/06/18/the-tipping-point/
+ https://www.quicklogic.com/blog/
+ https://www.quicklogic.com/2020/09/15/why-open-source-ecosystems-make-good-business-sense/
+ https://www.quicklogic.com/qorc/
+ https://en.wikipedia.org/wiki/RAD750
+ The RAD750 system has a price that is comparable to the RAD6000, the latter of which as of 2002 was listed at US$200,000 (equivalent to $284,292 in 2019).
+ https://theamphour.com/525-open-fpga-toolchains-and-machine-learning-with-brian-faith-of-quicklogic/
+ https://github.blog/2021-03-22-open-innovation-winning-strategy-digital-sovereignty-human-progress/
+ https://github.com/olofk/edalize
+ https://github.com/hdl/containers
+ https://twitter.com/OlofKindgren/status/1374848733746192394
+ You might also want to check out https://umarcor.github.io/osvb/index.html
+ https://www.linkedin.com/pulse/1932021-python-now-replaces-tcl-all-besteda-apis-avidan-efody/
+ “TCL has served us well, over the years, allowing us to provide an API, and at the same time ensure nobody will ever use it. I will miss it”.
+ https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/comb-full-adder.html
+ https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/carry4.html
+ FuseSoC is used by MicroWatt and Western Digital cores
+ OpenTitan also uses FuseSoC
+ LowRISC is UK based
+ https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
+ https://cirosantilli.com/x86-paging
+ https://stackoverflow.com/questions/18431261/how-does-x86-paging-work
+ http://denninginstitute.com/modules/vm/red/i486page.html
+ https://m.slashdot.org/story/391021 - mirror neural atrophy results in destruction of empathy
+```
projects / libreriscv.git / blobdiff