extraneous spelling correction

[libreriscv.git] / shakti / m_class / AXI.mdwn

diff --git a/shakti/m_class/AXI.mdwn b/shakti/m_class/AXI.mdwn
index bb1827f511c182f706cabf224c3d82e662e5ea3b..48c152953206b32336ecac2e2777d8e219aebfc7 100644 (file)
--- a/shakti/m_class/AXI.mdwn
+++ b/shakti/m_class/AXI.mdwn
@@ -4,3 +4,8 @@ See also [[wishbone]] Bus
 
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=10>
 * <https://github.com/alexforencich/verilog-axis>
+* <https://github.com/qermit/WishboneAXI/tree/master/cores/Wishbone2AXI/hdl>
+
+# AXI4 in migen
+
+* <https://github.com/peteut/migen-axi>