* <http://bugs.libre-riscv.org/show_bug.cgi?id=10>
* <https://github.com/alexforencich/verilog-axis>
-* https://github.com/qermit/WishboneAXI/tree/master/cores/Wishbone2AXI/hdl
+* <https://github.com/qermit/WishboneAXI/tree/master/cores/Wishbone2AXI/hdl>
+
+# AXI4 in migen
+
+* <https://github.com/peteut/migen-axi>