(no commit message)

[libreriscv.git] / shakti / m_class / UART.mdwn

diff --git a/shakti/m_class/UART.mdwn b/shakti/m_class/UART.mdwn
index f54f0128741706568d42b58d18ce82b528342b44..66ae630235fe73228500cde10bb41c66c2ded739 100644 (file)
--- a/shakti/m_class/UART.mdwn
+++ b/shakti/m_class/UART.mdwn
@@ -5,4 +5,4 @@ Several pages on opencores, including:
 * <https://opencores.org/projects/uart16550> which has wishbone
 * <https://github.com/freecores/uart16550> freecores version (basically same as above)
 * <https://git.m-labs.hk/M-Labs/HeavyX/src/branch/master/heavycomps/heavycomps/uart.py>
-
+* <https://github.com/antonblanchard/lpcperipheral/blob/master/lpcperipheral/lpcfront.py>