update UART page

[libreriscv.git] / shakti / m_class / UART.mdwn

diff --git a/shakti/m_class/UART.mdwn b/shakti/m_class/UART.mdwn
index f4db6db74b67d0da08b4a1d86b739fc21d42b006..f54f0128741706568d42b58d18ce82b528342b44 100644 (file)
--- a/shakti/m_class/UART.mdwn
+++ b/shakti/m_class/UART.mdwn
@@ -1,3 +1,8 @@
-# UART RTL
+# UART 16550
 
+Several pages on opencores, including:
+
+* <https://opencores.org/projects/uart16550> which has wishbone
+* <https://github.com/freecores/uart16550> freecores version (basically same as above)
 * <https://git.m-labs.hk/M-Labs/HeavyX/src/branch/master/heavycomps/heavycomps/uart.py>
+