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[libreriscv.git] / shakti / m_class / ULPI.mdwn

diff --git a/shakti/m_class/ULPI.mdwn b/shakti/m_class/ULPI.mdwn
index 12fe9e789faaeed833f9a275f065c4440dab0168..b475026c249c6cddcefe7b3e0e6d16187043c638 100644 (file)
--- a/shakti/m_class/ULPI.mdwn
+++ b/shakti/m_class/ULPI.mdwn
@@ -1,7 +1,30 @@
 # USB2 (ULPI)
 
-* <https://opencores.org/project,ulpi_wrapper>
+## Requirements
+* PHY (to be determined) <https://www.ti.com/product/TUSB1210>
+* DDR mode
+* ...
+* USB3300 breakout https://www.waveshare.com/usb3300-usb-hs-board.htm
+
+## LICENSE
+BSD I guess...(fix me)
+
+## Useful resources
+
+![UTMI_interface](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_bb.JPG)
+
+![UTMI+levels](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_aa.JPG)
+
+![UTMI+level3_interface](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_cc.JPG)
+
+![LPI_signals](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_dd.JPG)
+
+![LPI_signals_table](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_dd.JPG)
+
+## reference
+* <https://opencores.org/project,ulpi_wrapper> (GPL'd)
+* <https://github.com/mossmann/daisho/blob/master/sw/fpga/common/usb3/usb2_ulpi.v> (BSD)
 * <https://opencores.org/project,usb>
 * <https://github.com/alexforencich/verilog-wishbone>
-
+* <https://github.com/www-asics-ws/usb2_dev>