add slids

[libreriscv.git] / shakti / m_class / libre_riscv_chennai_2018.tex

diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex
index 536afd6e3e170cf394aca8d8a40b268268cd60e4..47afd4dc8779024b734264aec7ec79dbbdac8e9b 100644 (file)
--- a/shakti/m_class/libre_riscv_chennai_2018.tex
+++ b/shakti/m_class/libre_riscv_chennai_2018.tex
@@ -273,7 +273,7 @@
   \end{itemize}
    {\it Jacob Bachmeyer's Cache-control proposal turns L1 Cache into
    scratchpad RAM.  RVV is just too heavy (sorry!), Simple-V much
-   more light-weight and flexible.
+   more light-weight and flexible ($O(1)$ ISA proliferation)
    }
 }
 
@@ -289,7 +289,20 @@
 \frame{\frametitle{Summary}
 
  \begin{itemize}
-   \item TODO
+   \item Making a commercially-desirable SoC is neither academically
+         nor standard-investor sexy!  No AI. Boring. zzzz
+   \item Luckily there is an anonymous sponsor who needs an SoC that
+            doesn't exist (who knows the commercial benefits of Libre)
+   \item Shakti Group know the benefits (cost, sovereignty) of a Libre
+         Mobile-Class SoC as well (No spying on India citizens!)
+   \item A Libre GPU, even a modest performer (100T/s etc.) 
+            is the biggest technical risk/unknown (besides DDR3/4).\\
+            (fall-back is GC800. Do please help with a Libre GPU!)
+    \item DDR3/4 and eMMC are the main high-risk interfaces\\
+            (there are fall-back strategies in place)
+       \item Ultimately the strategy is all about cost reduction
+             vs risk mitigation,
+             with Libre/Ethical prioritised over "convenience"
   \end{itemize}
 }
 
@@ -303,7 +316,7 @@
   \end{center}
   
   \begin{itemize}
-       \item Discussion: 
+       \item Contact: lkcl@lkcl.net 
        \item http://libre-riscv.org/shakti/m\_class/
   \end{itemize}
 }