add slides

[libreriscv.git] / shakti / m_class / libre_riscv_chennai_2018.tex

diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex
index 47afd4dc8779024b734264aec7ec79dbbdac8e9b..a65a0d869d9975010b43d50f10f2bd47495fd4df 100644 (file)
--- a/shakti/m_class/libre_riscv_chennai_2018.tex
+++ b/shakti/m_class/libre_riscv_chennai_2018.tex
@@ -27,11 +27,14 @@
 \frame{\frametitle{Credits and Acknowledgements}
 
  \begin{itemize}
-   \item The Designers of RISC-V\vspace{15pt}
-   \item The Shakti Group\vspace{15pt}
-   \item Prof. G S Madhusudan\vspace{15pt}
-   \item Neel Gala\vspace{15pt}
-   \item Rishabh Jain\vspace{15pt}
+   \item The Designers of RISC-V\vspace{8pt}
+   \item The RISC-V Foundation\vspace{8pt}
+   \item The Shakti Group, and IIT Madras RISE Group\vspace{8pt}
+   \item Prof. G S Madhusudan\vspace{8pt}
+   \item Neel Gala\vspace{8pt}
+   \item Rishabh Jain\vspace{8pt}
+   \item Members of the RISC-V Open Groups (SW/HW/ISA)\vspace{8pt}
+   \item Libre and Open Software and Hardware Communities
   \end{itemize}
 }
 
@@ -112,7 +115,7 @@
  \begin{itemize}
    \item Cover a lot of different scenarios (embedded, tablets, industrial,
          netbooks, crypto-currency mining).
-       \item Decent performance with high efficiency.  RISC-V: 40 \%
+       \item Decent performance with high efficiency.  RISC-V: 40\%
                  more efficient than ARM / Intel.  Shakti a good
              candidate: 2.5ghz and 120mW per core @ 22nm.
        \item 1080p video: y'all gotta watch cute kittens on youtube, right?
@@ -220,7 +223,7 @@
  \begin{itemize}
    \item DDR3/4 PHYs are analog and very high speed.
                   Impedance training.  Extreme timing tolerances on parallel buses.\\
-                  No surprise they cost USD \$1m and above.
+                  No surprise proprietary cost is USD \$1m and above.
    \item Symbiotic EDA will do (Libre) PHY layout for USD \$300k,
             time to completion for chosen geometry: 8-12 months.
   \end{itemize}
@@ -257,7 +260,29 @@
 }
 
 
-\frame{\frametitle{Challenging Stuff [3] - Libre 3D GPU.  Sigh.}
+\frame{\frametitle{Challenging Stuff [3] - Power Management}
+
+ \begin{itemize}
+   \item Been done before (many times), but not as a Libre Design.
+   \item Sanjay Charagulla: GlobalFoundries 22nm mobile process
+            can reach as low as 0.4v
+   \item GPIO Banks need per-bank VREF (1.8v? to 3.3v)\\
+             IO pads need built-in
+            level-shifting to convert to CPU VCORE
+   \item Each core needs independent variable-voltage capability
+            and independent shut-down (PMIC supplies external voltage)
+   \item DDR RAM still needs refreshing (even in sleep mode)
+   \item Extra RV32 (PicoRV32?) always-on core for wake-up / RTC?
+   \item PLLs are Analog.  fun fun fun in the sun sun sun...
+  \end{itemize}
+   {\it Really need help.  PLLs, Analog stuff: specific
+          domain expertise.  Fall-back example:
+          https://www.dolphin-integration.com?
+   }
+}
+
+
+\frame{\frametitle{Challenging Stuff [4] - Libre 3D GPU.  Sigh.}
 
  \begin{itemize}
    \item Actual requirements quite modest: 30MP/s 100MT/s 5GFLOPS
@@ -278,6 +303,48 @@
 }
 
 
+\frame{\frametitle{Challenging Stuff [5] - Custom Extensions}
+
+ \begin{itemize}
+   \item GPUs are usually done with incompatible ISAs and effectively
+            doing OpenGL over IPC / RPC (Remote Procedure Calls)
+   \item Much simpler: GPGPU "one ISA" approach.  Custom-extend the 
+            core ISA to handle 3D, use Gallium3D-LLVM. 
+   \item Now add Video Extensions. and SIMD etc and
+          {\bf we are well beyond the only 2 available 32-bit custom opcodes}
+   \item Due to the Libre nature of this project, the custom opcode
+            space will be "dominated" by 
+            high-profile public hard-forks of gcc, binutils, llvm etc.
+            Which isn't going to go down well.
+   \item ISA "Conflict Resolution" is therefore absolutely critical\\
+            http://libre-riscv.org/isa\_conflict\_resolution/
+  \end{itemize}
+   {\it Remember Altivec. Learn from Intel.
+   \underline{This is everyone's problem.}
+   }
+}
+
+
+\frame{\frametitle{Interesting Missing Stuff [1] - Pinmux}
+
+ \begin{itemize}
+   \item Pinmux: multiplexer of functions onto pins\\
+            {\it DRAM Cell != DDR3/4, Mux Cell != Muxer}
+   \item Strategically extremely important to Commercial SoC success\\
+            STMicro, Rockchip, Freescale, Samsung, {\bf EVERYONE}
+   \item Bizarrely, a libre-licensed multi-way Pinmux doesn't exist.\\
+         {\it not on anyone's radar. at all.}
+         SiFive IOF not enough.
+   \item Verification (scenario analysis) and auto-generation of
+                TRM, header files, device-tree files, pretty much everything
+                makes sense (to any "lazy" Software Engineer...)
+   \item Corporations with their own pinmux unlikely to be interested.
+   \item http://git.libre-riscv.org/?p=pinmux.git \\
+         http://hands.com/~lkcl/pinmux\_chennai\_2018.pdf
+  \end{itemize}
+}
+
+
 \frame{\frametitle{TODO}
 
  \begin{itemize}