\frame{\frametitle{Credits and Acknowledgements}
\begin{itemize}
- \item The Designers of RISC-V\vspace{15pt}
- \item The Shakti Group\vspace{15pt}
- \item Prof. G S Madhusudan\vspace{15pt}
- \item Neel Gala\vspace{15pt}
- \item Rishabh Jain\vspace{15pt}
+ \item The Designers of RISC-V\vspace{8pt}
+ \item The RISC-V Foundation\vspace{8pt}
+ \item The Shakti Group, and IIT Madras RISE Group\vspace{8pt}
+ \item Prof. G S Madhusudan\vspace{8pt}
+ \item Neel Gala\vspace{8pt}
+ \item Rishabh Jain\vspace{8pt}
+ \item Members of the RISC-V Open Groups (SW/HW/ISA)\vspace{8pt}
+ \item Libre and Open Software and Hardware Communities
\end{itemize}
}
}
-\frame{\frametitle{Does what we want already exist?}
+\frame{\frametitle{Does what we want already exist? Surely this is nonsense!}
\begin{center}
\includegraphics[height=2.4in]{nolibresocs.jpg}\\
{\bf Analysis of SoCs over the past 7+ years (answer: no)}
}
-\frame{\frametitle{What's the problem?}
+\frame{\frametitle{Breakdown of non-existence of fully-Libre SoCs}
\begin{itemize}
\item {\bf iMX6}: Libre bootable, Vivante 3D GPU (libre etnaviv)
}
-\frame{\frametitle{So what's needed? What would a good (Libre) SoC have?}
+\frame{\frametitle{What would a good (Libre) boring, mundane SoC have?}
\begin{itemize}
\item Cover a lot of different scenarios (embedded, tablets, industrial,
netbooks, crypto-currency mining).
- \item Decent performance with high efficiency. RISC-V: 40 \%
+ \item Decent performance with high efficiency. RISC-V: 40\%
more efficient than ARM / Intel. Shakti a good
candidate: 2.5ghz and 120mW per core @ 22nm.
\item 1080p video: y'all gotta watch cute kittens on youtube, right?
and helping others fulfil their needs and goals)
\end{itemize}
{\it Detachment from the goal also helps. If someone else makes this
- product then GREAT! I can go do something else}
+ product then GREAT! I can go do something else}\\
+ \vspace{4pt}
+ {\bf Main point: please do not automatically assume Ethical and Libre is
+ non-commercial. It's not nice, and it's not helping }
}
}
+\frame{\frametitle{Challenging Stuff [1] - Memory Interfaces}
+
+ \begin{itemize}
+ \item DDR3/4 PHYs are analog and very high speed.
+ Impedance training. Extreme timing tolerances on parallel buses.\\
+ No surprise proprietary cost is USD \$1m and above.
+ \item Symbiotic EDA will do (Libre) PHY layout for USD \$300k,
+ time to completion for chosen geometry: 8-12 months.
+ \end{itemize}
+ {\it Silicon-proven but still risky. What are the alternatives?}
+ \vspace{4pt}
+ \begin{itemize}
+ \item 133mhz 32-bit SDRAM (um...) maybe even FlexBus?
+ \item HyperRAM (aka JEDEC xSPI) 8-bit SPI 166mhz or DDR-300.\\
+ 300mbyte/sec for only 13 wires, not bad! (We'll take several)\\
+ http://libre-riscv.org/shakti/m\_class/HyperRAM/
+ \item HMC: insanely fast, very low power. OpenHMC (LGPL)
+ https://opencores.org/project/openhmc
+ \end{itemize}
+}
+
+
+\frame{\frametitle{Challenging Stuff [2] - Video Decode Engine}
+
+ \begin{itemize}
+ \item Richard Herveille's Video Core Blocks\\
+ https://opencores.org/project/video\_systems
+ \item Symbiotic EDA MP4 decoder in FPGA
+ \item H.264 seems to have been done...\\
+ https://github.com/adsc-hls/synthesizable\_h264
+ \item Really needs SIMD (or better, not-SIMD)\\
+ {http://libre-riscv.org/simple\_v\_extension/}
+ \item Definitely needs xBitManip (parallelised by Simple-V)\\
+ https://github.com/cliffordwolf/xbitmanip
+ \end{itemize}
+ {\it SIMD is insane. $O(N^6)$ opcode proliferation. See\\
+ https://www.sigarch.org/simd-instructions-considered-harmful/ \\
+ (1): P-Ext designed for Audio. (2): Investigate RI5CY's SIMD
+ }
+}
+
+
+\frame{\frametitle{Challenging Stuff [3] - Power Management}
+
+ \begin{itemize}
+ \item Been done before (many times), but not as a Libre Design.
+ \item Sanjay Charagulla: GlobalFoundries 22nm mobile process
+ can reach as low as 0.4v
+ \item GPIO Banks need per-bank VREF (1.8v? to 3.3v)\\
+ IO pads need built-in
+ level-shifting to convert to CPU VCORE
+ \item Each core needs independent variable-voltage capability
+ and independent shut-down (PMIC supplies external voltage)
+ \item DDR RAM still needs refreshing (even in sleep mode)
+ \item Extra RV32 (PicoRV32?) always-on core for wake-up / RTC?
+ \item PLLs are Analog. fun fun fun in the sun sun sun...
+ \end{itemize}
+ {\it Really need help. PLLs, Analog stuff: specific
+ domain expertise. Fall-back example:
+ https://www.dolphin-integration.com?
+ }
+}
+
+
+\frame{\frametitle{Challenging Stuff [4] - Libre 3D GPU. Sigh.}
+
+ \begin{itemize}
+ \item Actual requirements quite modest: 30MP/s 100MT/s 5GFLOPS
+ but power/area is crucial ($2mm^2$ @ 40nm)
+ \item Nyuzi, MIAOW, GPLGPU (Number Nine), OGP.
+ \item Nyuzi based on Larrabee. Jeff Bush really helpful.
+ \item MIAOW is an OpenCL engine. GPLGPU is fixed-function
+ \item Nyuzi lessons: Software-only rendering not enough.
+ Getting through L1 cache takes most power. Fixed functions
+ such as parallel FP-Quad to ARGB Pixel, and Z-Buffer
+ needed.
+ \item Fallback is GC800 (\$250k) {\it contact me if you can do better!}
+ \end{itemize}
+ {\it Jacob Bachmeyer's Cache-control proposal turns L1 Cache into
+ scratchpad RAM. RVV is just too heavy (sorry!), Simple-V much
+ more light-weight and flexible ($O(1)$ ISA proliferation)
+ }
+}
+
+
+\frame{\frametitle{Challenging Stuff [5] - Custom Extensions}
+
+ \begin{itemize}
+ \item GPUs are usually done with incompatible ISAs and effectively
+ doing OpenGL over IPC / RPC (Remote Procedure Calls)
+ \item Much simpler: GPGPU "one ISA" approach. Custom-extend the
+ core ISA to handle 3D, use Gallium3D-LLVM.
+ \item Now add Video Extensions. and SIMD etc and
+ {\bf we are well beyond the only 2 available 32-bit custom opcodes}
+ \item Due to the Libre nature of this project, the custom opcode
+ space will be "dominated" by
+ high-profile public hard-forks of gcc, binutils, llvm etc.
+ Which isn't going to go down well.
+ \item ISA "Conflict Resolution" is therefore absolutely critical\\
+ http://libre-riscv.org/isa\_conflict\_resolution/
+ \end{itemize}
+ {\it Remember Altivec. Learn from Intel.
+ \underline{This is everyone's problem.}
+ }
+}
+
+
+\frame{\frametitle{Interesting Missing Stuff [1] - Pinmux}
+
+ \begin{itemize}
+ \item Pinmux: multiplexer of functions onto pins\\
+ {\it DRAM Cell != DDR3/4, Mux Cell != Muxer}
+ \item Strategically extremely important to Commercial SoC success\\
+ STMicro, Rockchip, Freescale, Samsung, {\bf EVERYONE}
+ \item Bizarrely, a libre-licensed multi-way Pinmux doesn't exist.\\
+ {\it not on anyone's radar. at all.}
+ SiFive IOF not enough.
+ \item Verification (scenario analysis) and auto-generation of
+ TRM, header files, device-tree files, pretty much everything
+ makes sense (to any "lazy" Software Engineer...)
+ \item Corporations with their own pinmux unlikely to be interested.
+ \item http://git.libre-riscv.org/?p=pinmux.git \\
+ http://hands.com/~lkcl/pinmux\_chennai\_2018.pdf
+ \end{itemize}
+}
+
+
\frame{\frametitle{TODO}
\begin{itemize}
\frame{\frametitle{Summary}
\begin{itemize}
- \item TODO
+ \item Making a commercially-desirable SoC is neither academically
+ nor standard-investor sexy! No AI. Boring. zzzz
+ \item Luckily there is an anonymous sponsor who needs an SoC that
+ doesn't exist (who knows the commercial benefits of Libre)
+ \item Shakti Group know the benefits (cost, sovereignty) of a Libre
+ Mobile-Class SoC as well (No spying on India citizens!)
+ \item A Libre GPU, even a modest performer (100T/s etc.)
+ is the biggest technical risk/unknown (besides DDR3/4).\\
+ (fall-back is GC800. Do please help with a Libre GPU!)
+ \item DDR3/4 and eMMC are the main high-risk interfaces\\
+ (there are fall-back strategies in place)
+ \item Ultimately the strategy is all about cost reduction
+ vs risk mitigation,
+ with Libre/Ethical prioritised over "convenience"
\end{itemize}
}
\end{center}
\begin{itemize}
- \item Discussion:
+ \item Contact: lkcl@lkcl.net
\item http://libre-riscv.org/shakti/m\_class/
\end{itemize}
}
projects / libreriscv.git / blobdiff