Missed a few...

[libreriscv.git] / shakti / m_class / pinmux.mdwn

diff --git a/shakti/m_class/pinmux.mdwn b/shakti/m_class/pinmux.mdwn
index 58752bb61aad425760391c3fe64fd11424468791..967dc6918d07f657015b832d7738ad9afc3fd5a8 100644 (file)
--- a/shakti/m_class/pinmux.mdwn
+++ b/shakti/m_class/pinmux.mdwn
@@ -14,14 +14,14 @@ Surprisingly complex!
 
 "to create a general-purpose libre-licensed pinmux
 module that can be used with a wide range of interfaces that have
-Open-Drain, Push-Push *and bi-directional* capabilities, as well as
+Open-Drain, Push-Pull *and bi-directional* capabilities, as well as
 optional pull-up and pull-down resistors, in an IDENTICAL fashion to
 that of ALL major well-known embedded SoCs from ST Micro, Cypress,
 Texas Instruments, NXP, Rockchip, Allwinner and many many others".
 
 * The IO pad shall have pull-up enable, pull-down enable, variable
   frequency de-bounce (schmidt trigger), tri-state capability, 
-  variable current drive (on input), Open Drain and CMOS Push-Push.
+  variable current drive (on input), Open Drain and CMOS Push-Pull.
 * Certain functions shall have the ability to control whether
   IO pads will be input or output (not the GPIO registers).
 * Number of wires shall be minimised especially in cases where
@@ -63,10 +63,6 @@ Introductions:
   and currently responsible for coordinating the design of a fully Libre
   RISC-V SoC in collaboration with the RISE Group, IIT Madras, Shakti Project.
   not much experience at verilog (have done a couple of tutorials).
-* Xing GUO(xing) - undergraduate (3rd year) from Southeast
-  University, EE student, C/C++, Python, Verilog, assembly (not very proficient), 
-  Haskell (not very proficient). RTL design, server maintenance.
-  E-mail: higuoxing at gmail dot com, Github: [Higuoxing](https://github.com/higuoxing) some of my projects are there :)
 * Aurojyoti Das(auro) - graduate student (MSc Electrical - Microelectronics) 
   at TU Delft, Netherlands. C/C++, Verilog, VHDL, SystemVerilog, RTL Design, 
   Logic Verification, Python/Perl/Shell scripting, Analog IC Design (currently learning) 
@@ -74,7 +70,7 @@ Introductions:
 Hardware available:
 
 * lkcl: ZC706
-* xing: zynq-7020 and Xilinx XC7A100T-484
+* xing: zynq-7020 and Xilinx XC7A100T-484 if needed contact him! <higuoxing@gmail.com>
 
 # Discussion and Links
 
@@ -89,6 +85,7 @@ Hardware available:
 * <https://github.com/xfguo/tbgen/blob/master/tbgen.py> auto-generated test module for verilog
 * <https://github.com/kdurant/verilog-testbench> described here <https://www.vim.org/scripts/script.php?script_id=4596>
 * <http://agilesoc.com/open-source-projects/svunit/> - SVunit - unit testing for verilog
+* [FPGA Overview](http://www.springer.com/cda/content/document/cda_downloaddocument/9781461435938-c2.pdf?SGWID=0-0-45-1333135-p174308376) Useful in writing GPIO related codes...
 
 # Pinouts Specification
 
@@ -137,14 +134,14 @@ Relying on this capability, however, by selecting a fixed voltage for
 the entire SoC's GPIO domain, is simply not a good idea: all sensors
 and peripherals which do not have a variable (VREF) capability for the
 logic side, or coincidentally are not at the exact same fixed voltage,
-will simply not be compatible if they are high-speed CMOS-level push-push
+will simply not be compatible if they are high-speed CMOS-level push-pull
 driven.  Open-Drain on the other hand can be handled with a MOSFET for
 two-way or even a diode for one-way depending on the levels, but this means
 significant numbers of external components if the number of lines is large.
 
 So, selecting a fixed voltage (such as 1.8v or 3.3v) results in a bit of a
 problem: external level-shifting is required on pretty much absolutely every
-single pin, particularly the high-speed (CMOS) push-push I/O.  An example: the
+single pin, particularly the high-speed (CMOS) push-pull I/O.  An example: the
 DM9000 is best run at 3.3v.  A fixed 1.8v FlexBus would
 require a whopping 18 pins (possibly even 24 for a 16-bit-wide bus)
 worth of level-shifting, which is not just costly