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[libreriscv.git] / shakti / m_class.mdwn

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index 63e288b2ac0331318a3eaa9d7b23a8a9fc6036d2..1e5ee0b6faebb4089fe7f5b9fe39ac215fe94b27 100644 (file)
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -11,11 +11,12 @@ yields.
 * See [[peripheralschematics]] for example Reference Layouts
 * See [[ramanalysis]] for a comprehensive analysis of why DDR3 is to be used.
 * See [[todo]] for a rough list of tasks (and link to bugtracker)
+* <https://bugs.libre-soc.org/show_bug.cgi?id=2>
 
 ## Rough specification.
 
-Quad-core 28nm RISC-V 64-bit (RISCV64GC core with Vector SIMD Media / 3D
-extensions), 300-pin 15x15mm BGA 0.8mm pitch, 32-bit DDR3/DDR3L/LPDDR3
+Quad-core 28nm OpenPOWER 64-bit (OpenPOWER v3.0B core with Simple-V Vector Media / 3D
+extensions), 300-pin 15x15mm BGA 0.8mm pitch, 32-bit DDR3-4/LPDDR3/4
 memory interface and libre / open interfaces and accelerated hardware
 functions suitable for the higher-end, low-power, embedded, industrial
 and mobile space.
@@ -40,7 +41,7 @@ The only barrier to being able to replicate the masks from scratch
 is the proprietary cells (e.g. memory cells) designed by the Foundries:
 there is a potential long-term strategy in place to deal with that issue.
 
-The only proprietary interface utilised in the entire SoC is the DDR3
+The only proprietary interface utilised in the entire SoC is the DDR3/4
 PHY plus Controller, which will be replaced in a future revision, making
 the entire SoC exclusively designed and made from fully libre-licensed
 BSD and LGPL openly and freely accessible VLSI and VHDL source.
@@ -48,7 +49,7 @@ BSD and LGPL openly and freely accessible VLSI and VHDL source.
 In addition, no proprietary firmware whatsoever will be required to
 operate or boot the device right from the bedrock: the entire software
 stack will also be libre-licensed (even for programming the initial
-proprietary DDR3 PHY+Controller)
+proprietary DDR3/4 PHY+Controller)
 
 # Inspiration from several sources
 
@@ -99,7 +100,7 @@ firmly a priority focus.
 
 ## Common Peripherals to majority of target markets
 
-* SPI or 8080 or RGB/TTL or LVDS LCD display.  SPI: 320x240.  LVDS: 1440x900.
+* SPI or 8080 or [RGB/TTL](RGBTTL) or LVDS LCD display.  SPI: 320x240.  LVDS: 1440x900.
 * LCD Backlight, requires GPIO power-control plus PWM for brightness control
 * USB-OTG Port (OTG-Host, OTG Client, Charging capability)
 * Baseband Modem (GSM / GPRS / 3G / LTE) requiring USB, UART, and PCM audio
@@ -119,6 +120,8 @@ firmly a priority focus.
 * Real-time Clock (usually an I2C device but may be on-board a support MCU)
 * [[PCIe]] via PXPIPE
 * [[LPC]] from Raptor Engineering
+* [[USB3]]
+* [[RGMII]] Gigabit Ethernet
 
 ## Peripherals unique to laptop market
 
@@ -127,13 +130,13 @@ firmly a priority focus.
 
 ## Peripherals common to laptop and Industrial Market
 
-* Ethernet (RGMII or better 8080-style XT/AT/ATI MCU bus)
+* Ethernet ([[RGMII]] or better 8080-style XT/AT/ATI MCU bus for e.g. DM9000)
 
 ## Augmentation by an embedded MCU
 
 Some functions, particularly analog, are particularly tricky to implement
-in an early SoC.  In addition, CAN is still patented.  For unusual, patented
-or analog functionality such as CAN, RTC, ADC, DAC, SPDIF, One-wire Bus
+in an early SoC.  In addition, CAN is still patented (not any more).  For unusual, patented
+or analog functionality such as RTC, ADC, DAC, SPDIF, One-wire Bus
 and so on it is easier and simpler to deploy an ultra-low-cost low-speed
 companion Micro-Controller such as the crystal-less STMS8003 ($0.24) or
 the crystal-less STM32F072 or other suitable MCU, depending on requirements.
@@ -176,15 +179,18 @@ image acceleration, scalable fonts, and Z-buffering and much more.
 
 <https://opencores.org/project,orsoc_graphics_accelerator>
 
+<https://github.com/m-labs/milkymist/tree/master/cores/tmu2>
+
 ### 3D acceleration
 
 * MIAOW: ATI-compatible shader engine <http://miaowgpu.org/>
 * ORSOC GPU contains some primitives that can be used
-* SIMD RISC-V extensions can obviate the need for a "full" separate GPU
+* Simple-V Vector extensions can obviate the need for a "full" separate GPU
 * Nyuzi (OpenMP, based on Intel Larabee Compute Engine)
 * Rasteriser <https://github.com/jbush001/ChiselGPU/tree/master/hardware>
 * OpenShader <https://git.code.sf.net/p/openshader/code>
 * GPLGPU <https://github.com/asicguy/gplgpu>
+* FlexGripPlus <https://github.com/Jerc007/Open-GPGPU-FlexGrip->
 
 ### Video encode / decode
 
@@ -211,14 +217,14 @@ TBD
 * 2x 1-lane [[SPI]]
 * 1x 4-lane (quad) [[QSPI]]
 * 4x SD/MMC (1x 1/2/4/8-bit, 3x 1/2/4-bit)
-* 2x full UART incl. CTS/RTS
-* 3x UART (TX/RX only)
+* 2x full [[UART]] incl. CTS/RTS
+* 3x [[UART]] (TX/RX only)
 * 3x [[I2C]] (in case of address clashes between peripherals)
 * 8080-style AT/XT/ATI MCU Bus Interface, with multiple (8x CS#) lines
 * 3x [[PWM]]-capable GPIO
 * 32x [[EINT]]-cable GPIO with full edge-triggered and low/high IRQ capability
 * 1x [[I2S]] audio with 4-wire output and 1-wire input.
-* 3x USB2 (ULPI for reduced pincount) each capable of USB-OTG support
+* 3x [[USB2]] ([[ULPI]] for reduced pincount) each capable of USB-OTG support
 * [[DDR]] DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
 * [[JTAG]] for debugging
 
@@ -251,6 +257,7 @@ List of Interfaces:
 * Pin Multiplexing [[pinmux]]
 * Gigabit Ethernet [[RGMII]]
 * SDRAM [[sdram]]
+* [[SRAM]] Cell 
 
 List of Internal Interfaces: