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[libreriscv.git] / shakti / m_class.mdwn

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index ecad472f1c6632761038a665234175b9afa7da63..3f3f7e0ec8d6d6348d979cb7b51750c9ca8d0de1 100644 (file)
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -15,7 +15,7 @@ yields.
 ## Rough specification.
 
 Quad-core 28nm RISC-V 64-bit (RISCV64GC core with Vector SIMD Media / 3D
-extensions), 300-pin 15x15mm BGA 0.8mm pitch, 32-bit DDR3/DDR3L/LPDDR3
+extensions), 300-pin 15x15mm BGA 0.8mm pitch, 32-bit DDR3-4/LPDDR3/4
 memory interface and libre / open interfaces and accelerated hardware
 functions suitable for the higher-end, low-power, embedded, industrial
 and mobile space.
@@ -40,7 +40,7 @@ The only barrier to being able to replicate the masks from scratch
 is the proprietary cells (e.g. memory cells) designed by the Foundries:
 there is a potential long-term strategy in place to deal with that issue.
 
-The only proprietary interface utilised in the entire SoC is the DDR3
+The only proprietary interface utilised in the entire SoC is the DDR3/4
 PHY plus Controller, which will be replaced in a future revision, making
 the entire SoC exclusively designed and made from fully libre-licensed
 BSD and LGPL openly and freely accessible VLSI and VHDL source.
@@ -48,7 +48,7 @@ BSD and LGPL openly and freely accessible VLSI and VHDL source.
 In addition, no proprietary firmware whatsoever will be required to
 operate or boot the device right from the bedrock: the entire software
 stack will also be libre-licensed (even for programming the initial
-proprietary DDR3 PHY+Controller)
+proprietary DDR3/4 PHY+Controller)
 
 # Inspiration from several sources
 
@@ -119,6 +119,7 @@ firmly a priority focus.
 * Real-time Clock (usually an I2C device but may be on-board a support MCU)
 * [[PCIe]] via PXPIPE
 * [[LPC]] from Raptor Engineering
+* [[USB3]]
 
 ## Peripherals unique to laptop market
 
@@ -127,7 +128,7 @@ firmly a priority focus.
 
 ## Peripherals common to laptop and Industrial Market
 
-* Ethernet (RGMII or better 8080-style XT/AT/ATI MCU bus)
+* Ethernet ([[RGMII]] or better 8080-style XT/AT/ATI MCU bus for e.g. DM9000)
 
 ## Augmentation by an embedded MCU
 
@@ -219,7 +220,7 @@ TBD
 * 3x [[PWM]]-capable GPIO
 * 32x [[EINT]]-cable GPIO with full edge-triggered and low/high IRQ capability
 * 1x [[I2S]] audio with 4-wire output and 1-wire input.
-* 3x USB2 (ULPI for reduced pincount) each capable of USB-OTG support
+* 3x [[USB2]] ([[ULPI]] for reduced pincount) each capable of USB-OTG support
 * [[DDR]] DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
 * [[JTAG]] for debugging