## Rough specification.
-Quad-core 28nm RISC-V 64-bit (RISCV64GC core with Vector SIMD Media / 3D
-extensions), 300-pin 15x15mm BGA 0.8mm pitch, 32-bit DDR3/DDR3L/LPDDR3
+Quad-core 28nm OpenPOWER 64-bit (OpenPOWER v3.0B core with Simple-V Vector Media / 3D
+extensions), 300-pin 15x15mm BGA 0.8mm pitch, 32-bit DDR3-4/LPDDR3/4
memory interface and libre / open interfaces and accelerated hardware
functions suitable for the higher-end, low-power, embedded, industrial
and mobile space.
[[shakti_libre_riscv.jpg]]
+## Die area estimates
+
+* <http://hwacha.org/papers/riscv-esscirc2014-talk.pdf>
+* 40nm 64-bit rocket single-core single-issue in-order: 0.14mm^2
+* 40nm 16-16k L1 caches, 0.25mm^2
+* <http://people.csail.mit.edu/beckmann/publications/tech.../grain_size_tr_feb_2010.pdf>
+
## Targetting full Libre Licensing to the bedrock.
The only barrier to being able to replicate the masks from scratch
is the proprietary cells (e.g. memory cells) designed by the Foundries:
there is a potential long-term strategy in place to deal with that issue.
-The only proprietary interface utilised in the entire SoC is the DDR3
+The only proprietary interface utilised in the entire SoC is the DDR3/4
PHY plus Controller, which will be replaced in a future revision, making
the entire SoC exclusively designed and made from fully libre-licensed
BSD and LGPL openly and freely accessible VLSI and VHDL source.
In addition, no proprietary firmware whatsoever will be required to
operate or boot the device right from the bedrock: the entire software
stack will also be libre-licensed (even for programming the initial
-proprietary DDR3 PHY+Controller)
+proprietary DDR3/4 PHY+Controller)
# Inspiration from several sources
## Common Peripherals to majority of target markets
-* SPI or 8080 or RGB/TTL or LVDS LCD display. SPI: 320x240. LVDS: 1440x900.
+* SPI or 8080 or [RGB/TTL](RGBTTL) or LVDS LCD display. SPI: 320x240. LVDS: 1440x900.
* LCD Backlight, requires GPIO power-control plus PWM for brightness control
* USB-OTG Port (OTG-Host, OTG Client, Charging capability)
* Baseband Modem (GSM / GPRS / 3G / LTE) requiring USB, UART, and PCM audio
* SD/MMC for external MicroSD
* SD/MMC for on-PCB eMMC (care needed on power/boot sequence)
* NAND Flash (not recommended), requires 8080/ATI-style Bus with dedicated CS#
-* Optional 4-wire SPI NAND/NOR for boot (XIP - Execute In-place - recommended).
+* Optional 4-wire [[QSPI]] NAND/NOR for boot (XIP - Execute In-place - recommended).
* Audio over [[I2S]] (5-pin: 4 for output, 1 for input), fall-back to USB Audio
* Audio also over [[AC97]]
* Some additional SPI peripherals, e.g. connection to low-power MCU.
* I2C sensors: accelerometer, compass, etc. Each requires EINT and RST GPIO.
* Capacitive Touchpanel (I2C and also requiring EINT and RST GPIO)
* Real-time Clock (usually an I2C device but may be on-board a support MCU)
+* [[PCIe]] via PXPIPE
+* [[LPC]] from Raptor Engineering
+* [[USB3]]
+* [[RGMII]] Gigabit Ethernet
## Peripherals unique to laptop market
## Peripherals common to laptop and Industrial Market
-* Ethernet (RGMII or better 8080-style XT/AT/ATI MCU bus)
+* Ethernet ([[RGMII]] or better 8080-style XT/AT/ATI MCU bus for e.g. DM9000)
## Augmentation by an embedded MCU
Some functions, particularly analog, are particularly tricky to implement
-in an early SoC. In addition, CAN is still patented. For unusual, patented
-or analog functionality such as CAN, RTC, ADC, DAC, SPDIF, One-wire Bus
+in an early SoC. In addition, CAN is still patented (not any more). For unusual, patented
+or analog functionality such as RTC, ADC, DAC, SPDIF, One-wire Bus
and so on it is easier and simpler to deploy an ultra-low-cost low-speed
companion Micro-Controller such as the crystal-less STMS8003 ($0.24) or
the crystal-less STM32F072 or other suitable MCU, depending on requirements.
<https://opencores.org/project,orsoc_graphics_accelerator>
+<https://github.com/m-labs/milkymist/tree/master/cores/tmu2>
+
### 3D acceleration
* MIAOW: ATI-compatible shader engine <http://miaowgpu.org/>
* ORSOC GPU contains some primitives that can be used
-* SIMD RISC-V extensions can obviate the need for a "full" separate GPU
+* Simple-V Vector extensions can obviate the need for a "full" separate GPU
+* Nyuzi (OpenMP, based on Intel Larabee Compute Engine)
+* Rasteriser <https://github.com/jbush001/ChiselGPU/tree/master/hardware>
+* OpenShader <https://git.code.sf.net/p/openshader/code>
+* GPLGPU <https://github.com/asicguy/gplgpu>
+* FlexGripPlus <https://github.com/Jerc007/Open-GPGPU-FlexGrip->
### Video encode / decode
* Plain [[GPIO]] multiplexed with a [[pinmux]] onto (nearly) all other pins
* RGB/TTL up to 1440x900 @ 60fps, 24-bit colour
-* 2x 1-lane SPI
-* 1x 4-lane (quad) SPI
+* 2x 1-lane [[SPI]]
+* 1x 4-lane (quad) [[QSPI]]
* 4x SD/MMC (1x 1/2/4/8-bit, 3x 1/2/4-bit)
-* 2x full UART incl. CTS/RTS
-* 3x UART (TX/RX only)
+* 2x full [[UART]] incl. CTS/RTS
+* 3x [[UART]] (TX/RX only)
* 3x [[I2C]] (in case of address clashes between peripherals)
* 8080-style AT/XT/ATI MCU Bus Interface, with multiple (8x CS#) lines
* 3x [[PWM]]-capable GPIO
* 32x [[EINT]]-cable GPIO with full edge-triggered and low/high IRQ capability
* 1x [[I2S]] audio with 4-wire output and 1-wire input.
-* 3x USB2 (ULPI for reduced pincount) each capable of USB-OTG support
-* DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
+* 3x [[USB2]] ([[ULPI]] for reduced pincount) each capable of USB-OTG support
+* [[DDR]] DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
+* [[JTAG]] for debugging
Some interfaces at:
* <https://github.com/sifive/freedom/blob/master/src/main/scala/everywhere/e300artydevkit/Platform.scala>
Pinmux ("IOF") for multiplexing several I/O functions onto a single pin
* <https://bitbucket.org/casl/c-class/src/0e77398a030bfd705930d0f1b8b9b5050d76e265/src/peripherals/?at=master>
- including AXI, DMA, GPIO, I2C, JTAG, PLIC, QSPI, SDRAM, UART (and TCM?). FlexBus, HyperBus and xSPI to
- be added.
+ including AXI, DMA, GPIO, I2C, JTAG, PLIC, QSPI, SDRAM, UART (and TCM?).
+ FlexBus, HyperBus and xSPI to be added.
List of Interfaces:
+* [[CSI]]
+* [[DDR]]
+* [[JTAG]]
* [[I2C]]
* [[I2S]]
* [[PWM]]
* [[FlexBus]]
* LCD / RGB/TTL [[RGBTTL]]
* [[SPI]]
+* [[QSPI]]
* SD/MMC and eMMC [[sdmmc]]
* Pin Multiplexing [[pinmux]]
* Gigabit Ethernet [[RGMII]]
+* SDRAM [[sdram]]
List of Internal Interfaces:
and software-emulate high-speed interfaces such as SATA, HDMI, PCIe and
many more.
+# Testing
+
+* cocotb
+* <https://github.com/aoeldemann/cocotb> cocotb AXI4 stream interface
+
# Research (to investigate)
+* LPC Interface <https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga>
* <https://level42.ca/projects/ultra64/Documentation/man/pro-man/pro25/index25.1.html>
* <http://n64devkit.square7.ch/qa/graphics/ucode.htm>
* <https://dac.com/media-center/exhibitor-news/synopsys%E2%80%99-designware-universal-ddr-memory-controller-delivers-30-percent> 110nm DDR3 PHY
+* <https://bitbucket.org/cfelton/minnesota> myhdl HDL cores
+* B Extension proposal <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/zi_7B15kj6s>
+* Bit-extracts <https://github.com/cliffordwolf/bextdep>
+* Bit-reverse <http://programming.sirrida.de/bit_perm.html#general_reverse_bits>
+* Bit-permutations <http://programming.sirrida.de/bit_perm.html#c_e>
+* Commentary on Micro-controller <https://github.com/emb-riscv/specs-markdown/blob/develop/improvements-upon-privileged.md>
+* P-SIMD <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/vYVi95gF2Mo>
+
+>
[[!tag cpus]]
-
projects / libreriscv.git / blobdiff