(no commit message)

[libreriscv.git] / shakti / m_class.mdwn

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index 71fea274dfaa2e27bd1980ab2133489bfde97004..91870f6864fa3ea1c5dc193b3fb19723a9808ad8 100644 (file)
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -117,6 +117,9 @@ firmly a priority focus.
 * I2C sensors: accelerometer, compass, etc.  Each requires EINT and RST GPIO.
 * Capacitive Touchpanel (I2C and also requiring EINT and RST GPIO)
 * Real-time Clock (usually an I2C device but may be on-board a support MCU)
+* [[PCIe]] via PXPIPE
+* [[LPC]] from Raptor Engineering
+* [[USB3]]
 
 ## Peripherals unique to laptop market
 
@@ -125,7 +128,7 @@ firmly a priority focus.
 
 ## Peripherals common to laptop and Industrial Market
 
-* Ethernet (RGMII or better 8080-style XT/AT/ATI MCU bus)
+* Ethernet ([[RGMII]] or better 8080-style XT/AT/ATI MCU bus for e.g. DM9000)
 
 ## Augmentation by an embedded MCU
 
@@ -183,6 +186,7 @@ image acceleration, scalable fonts, and Z-buffering and much more.
 * Rasteriser <https://github.com/jbush001/ChiselGPU/tree/master/hardware>
 * OpenShader <https://git.code.sf.net/p/openshader/code>
 * GPLGPU <https://github.com/asicguy/gplgpu>
+* FlexGripPlus <https://github.com/Jerc007/Open-GPGPU-FlexGrip->
 
 ### Video encode / decode
 
@@ -209,15 +213,15 @@ TBD
 * 2x 1-lane [[SPI]]
 * 1x 4-lane (quad) [[QSPI]]
 * 4x SD/MMC (1x 1/2/4/8-bit, 3x 1/2/4-bit)
-* 2x full UART incl. CTS/RTS
-* 3x UART (TX/RX only)
+* 2x full [[UART]] incl. CTS/RTS
+* 3x [[UART]] (TX/RX only)
 * 3x [[I2C]] (in case of address clashes between peripherals)
 * 8080-style AT/XT/ATI MCU Bus Interface, with multiple (8x CS#) lines
 * 3x [[PWM]]-capable GPIO
 * 32x [[EINT]]-cable GPIO with full edge-triggered and low/high IRQ capability
 * 1x [[I2S]] audio with 4-wire output and 1-wire input.
-* 3x USB2 (ULPI for reduced pincount) each capable of USB-OTG support
-* DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
+* 3x [[USB2]] ([[ULPI]] for reduced pincount) each capable of USB-OTG support
+* [[DDR]] DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
 * [[JTAG]] for debugging
 
 Some interfaces at:
@@ -234,6 +238,8 @@ Some interfaces at:
 
 List of Interfaces:
 
+* [[CSI]]
+* [[DDR]]
 * [[JTAG]]
 * [[I2C]]
 * [[I2S]]
@@ -348,10 +354,17 @@ many more.
 
 # Research (to investigate)
 
+* LPC Interface <https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga>
 * <https://level42.ca/projects/ultra64/Documentation/man/pro-man/pro25/index25.1.html>
 * <http://n64devkit.square7.ch/qa/graphics/ucode.htm>
 * <https://dac.com/media-center/exhibitor-news/synopsys%E2%80%99-designware-universal-ddr-memory-controller-delivers-30-percent> 110nm DDR3 PHY
 * <https://bitbucket.org/cfelton/minnesota> myhdl HDL cores
-
+* B Extension proposal <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/zi_7B15kj6s>
+* Bit-extracts <https://github.com/cliffordwolf/bextdep>
+* Bit-reverse <http://programming.sirrida.de/bit_perm.html#general_reverse_bits>
+* Bit-permutations <http://programming.sirrida.de/bit_perm.html#c_e>
+* Commentary on Micro-controller <https://github.com/emb-riscv/specs-markdown/blob/develop/improvements-upon-privileged.md>
+* P-SIMD <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/vYVi95gF2Mo>
+
+>
 [[!tag cpus]]
-