* 32x [[EINT]]-cable GPIO with full edge-triggered and low/high IRQ capability
* 1x [[I2S]] audio with 4-wire output and 1-wire input.
* 3x USB2 (ULPI for reduced pincount) each capable of USB-OTG support
-* DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
+* [[DDR]] DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
* [[JTAG]] for debugging
Some interfaces at:
List of Interfaces:
+* [[CSI]]
+* [[DDR]]
* [[JTAG]]
* [[I2C]]
* [[I2S]]
* <http://n64devkit.square7.ch/qa/graphics/ucode.htm>
* <https://dac.com/media-center/exhibitor-news/synopsys%E2%80%99-designware-universal-ddr-memory-controller-delivers-30-percent> 110nm DDR3 PHY
* <https://bitbucket.org/cfelton/minnesota> myhdl HDL cores
-
+* B Extension proposal <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/zi_7B15kj6s>
+* Bit-extracts <https://github.com/cliffordwolf/bextdep>
+* Bit-reverse <http://programming.sirrida.de/bit_perm.html#general_reverse_bits>
+* Bit-permutations <http://programming.sirrida.de/bit_perm.html#c_e>
+* Commentary on Micro-controller <https://github.com/emb-riscv/specs-markdown/blob/develop/improvements-upon-privileged.md>
+* P-SIMD <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/vYVi95gF2Mo>
+
+>
[[!tag cpus]]
-