re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / sidebar.mdwn

diff --git a/sidebar.mdwn b/sidebar.mdwn
index 3b2aec06a567600d669720e8d8beab4460764204..966433cf55a25160201f6d37ad1c802a3c5d3f4a 100644 (file)
--- a/sidebar.mdwn
+++ b/sidebar.mdwn
@@ -6,6 +6,7 @@
 | [Librecores][11]               |
 | [Libre-SOC Wikipedia][12]      |
 | [PyPI packages][13]            |
+| [Hackaday][14]                 |
 | [[conferences]]                |
 | [[HDL_workflow]]               |
 | [Simple-V OpenPOWER Draft](/openpower/sv/) |
@@ -43,3 +44,4 @@
 [11]: https://librecores.org/libre-soc
 [12]: https://en.wikipedia.org/wiki/Libre-SOC
 [13]: https://pypi.org/search/?q=libresoc
+[14]: https://hackaday.io/project/182547-the-libre-soc-project