re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / sidebar.mdwn

diff --git a/sidebar.mdwn b/sidebar.mdwn
index 96e0a4f90c84105e5f5cf030ef5686ce2ecb0bc4..966433cf55a25160201f6d37ad1c802a3c5d3f4a 100644 (file)
--- a/sidebar.mdwn
+++ b/sidebar.mdwn
@@ -1,17 +1,18 @@
 | Link                           |
 | --------                       |
 | [[Sitemap]]                    |
-| [Updates][9]          |
-| [OpenCollective][10]          |
-| [Librecores][11]          |
+| [Crowdsupply Updates][9]       |
+| [OpenCollective][10]           |
+| [Librecores][11]               |
 | [Libre-SOC Wikipedia][12]      |
-[ [PyPI packages][13]            |
+| [PyPI packages][13]            |
+| [Hackaday][14]                 |
 | [[conferences]]                |
 | [[HDL_workflow]]               |
 | [Simple-V OpenPOWER Draft](/openpower/sv/) |
 | [Documentation](/docs/) |
 | [Bugs and Tasks][2]            |
-| [Mailing Lists][3]             |
+| [All Mailing Lists][3]         |
 | [List Archives][4]             |
 | [Git repositories][5]          |
 | [Kazan (Vulkan driver)][6]     |
@@ -43,3 +44,4 @@
 [11]: https://librecores.org/libre-soc
 [12]: https://en.wikipedia.org/wiki/Libre-SOC
 [13]: https://pypi.org/search/?q=libresoc
+[14]: https://hackaday.io/project/182547-the-libre-soc-project