add decision-making section

[libreriscv.git] / simple_v_extension / simple_v_chennai_2018.tex

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 9b0207ecd02fa9bb5a7bad0d51560f1154e2c56b..6401ef90baabb53b6331dc7c0ee80c93cd52f6df 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -50,7 +50,7 @@
    https://sigarch.org/simd-instructions-considered-harmful
    \item Setup and corner-cases alone are extremely complex.\\
             Hardware is easy, but software is hell.
-   \item O($N^{6}$) ISA opcode proliferation!\\
+   \item O($N^{6}$) ISA opcode proliferation (1000s of instructions)\\
             opcode, elwidth, veclen, src1-src2-dest hi/lo
   \end{itemize}
 }
@@ -103,7 +103,7 @@
 \frame{\frametitle{What's the value of SV? Why adopt it even in non-V?}
 
  \begin{itemize}
-   \item memcpy becomes much smaller (higher bang-per-buck)
+   \item memcpy has a much higher bang-per-buck ratio
    \item context-switch (LOAD/STORE multiple): 1-2 instructions
    \item Compressed instrs further reduces I-cache (etc.)
    \item Reduced I-cache load (and less I-reads)
@@ -150,7 +150,7 @@
    \item Standard and future and custom opcodes now parallel\\
          (crucially: with NO extra instructions needing to be added)
   \end{itemize}
-  Note: EVERYTHING is parallelised:
+  Note: EVERY scalar op now paralleliseable
    \begin{itemize}
    \item All LOAD/STORE (inc. Compressed, Int/FP versions)
    \item All ALU ops (Int, FP, SIMD, DSP, everything)
@@ -370,9 +370,9 @@ for (i = 0; i < 16; i++) // 16 CSRs?
 \begin{semiverbatim}
 def get\_pred\_val(bool is\_fp\_op, int reg):
    tb = int\_pred if is\_fp\_op else fp\_pred
-   if (!tb[reg].enabled):
-      return ~0x0              // all ops enabled
-   predidx = tb[reg].predidx   // redirection occurs HERE
+   if (!tb[reg].enabled): return ~0x0 // all ops enabled
+   predidx  = tb[reg].predidx  // redirection occurs HERE
+   predidx += tb[reg].bank << 5 // 0 (1=rsvd)
    predicate = intreg[predidx] // actual predicate HERE
    if (tb[reg].inv):
       predicate = ~predicate   // invert ALL bits
@@ -471,10 +471,10 @@ def get\_pred\_val(bool is\_fp\_op, int reg):
 \begin{semiverbatim}
 function op\_add(rd, rs1, rs2) # add not VADD!
   int i, id=0, irs1=0, irs2=0;
+  predval = get\_pred\_val(FALSE, rd);
   rd  = int\_vec[rd ].isvector ? int\_vec[rd ].regidx : rd;
   rs1 = int\_vec[rs1].isvector ? int\_vec[rs1].regidx : rs1;
   rs2 = int\_vec[rs2].isvector ? int\_vec[rs2].regidx : rs2;
-  predval = get\_pred\_val(FALSE, rd);
   for (i = 0; i < VL; i++)
     if (predval \& 1<<i) # predication uses intregs
        ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];