clarify

[libreriscv.git] / simple_v_extension / simple_v_chennai_2018.tex

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 89247521945f952d2ceefd058e5b7f81878d6bae..7cd08ad85c1905d8b3737a2b3ccfae2d083aadd6 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -486,14 +486,16 @@ for (i = 0; i < 16; i++) // 16 CSRs?
 \frame{\frametitle{What's the downside(s) of SV?}
  \begin{itemize}
    \item EVERY register operation is inherently parallelised\\
-            (scalar ops are just vectors of length 1)\vspace{8pt}
+            (scalar ops are just vectors of length 1)\vspace{4pt}
    \item An extra pipeline phase is pretty much essential\\
-         for fast low-latency implementations\vspace{8pt}
+         for fast low-latency implementations\vspace{4pt}
    \item Assuming an instruction FIFO, N ops could be taken off\\
          of a parallel op per cycle (avoids filling entire FIFO;\\
-         also is less work per cycle: lower complexity / latency)\vspace{8pt}
+         also is less work per cycle: lower complexity / latency)\vspace{4pt}
    \item With zeroing off, skipping non-predicated elements is hard:\\
-         it is however an optimisation (and could be skipped).
+         it is however an optimisation (and could be skipped).\vspace{4pt}
+   \item Setting up the tables (interpreting the CSR key-value stores)\\
+            might be a bit complex to optimise.
   \end{itemize}
 }