add slides

[libreriscv.git] / simple_v_extension / simple_v_chennai_2018.tex

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 62f312fe8e9a73976ec66fb3f6e15cf770ebbc01..902f7cc22a4ca9583b362fa488bdd1fff3d17c54 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -150,7 +150,7 @@
    \item Standard and future and custom opcodes now parallel\\
          (crucially: with NO extra instructions needing to be added)
   \end{itemize}
-  Note: EVERYTHING is parallelised:
+  Note: EVERY scalar op now paralleliseable
    \begin{itemize}
    \item All LOAD/STORE (inc. Compressed, Int/FP versions)
    \item All ALU ops (Int, FP, SIMD, DSP, everything)
@@ -370,9 +370,9 @@ for (i = 0; i < 16; i++) // 16 CSRs?
 \begin{semiverbatim}
 def get\_pred\_val(bool is\_fp\_op, int reg):
    tb = int\_pred if is\_fp\_op else fp\_pred
-   if (!tb[reg].enabled):
-      return ~0x0              // all ops enabled
-   predidx = tb[reg].predidx   // redirection occurs HERE
+   if (!tb[reg].enabled): return ~0x0 // all ops enabled
+   predidx  = tb[reg].predidx  // redirection occurs HERE
+   predidx += tb[reg].bank << 5 // 0 (1=rsvd)
    predicate = intreg[predidx] // actual predicate HERE
    if (tb[reg].inv):
       predicate = ~predicate   // invert ALL bits