https://sigarch.org/simd-instructions-considered-harmful
\item Setup and corner-cases alone are extremely complex.\\
Hardware is easy, but software is hell.
- \item O($N^{6}$) ISA opcode proliferation!\\
+ \item O($N^{6}$) ISA opcode proliferation (1000s of instructions)\\
opcode, elwidth, veclen, src1-src2-dest hi/lo
\end{itemize}
}
\begin{itemize}
\item Effectively a variant of SIMD / SIMT (arbitrary length)\vspace{4pt}
+ \item Fascinatingly, despite being a SIMD-variant, RVV only has
+ O(N) opcode proliferation! (extremely well designed)
\item Extremely powerful (extensible to 256 registers)\vspace{4pt}
\item Supports polymorphism, several datatypes (inc. FP16)\vspace{4pt}
\item Requires a separate Register File (32 w/ext to 256)\vspace{4pt}
\item 98 percent opcode duplication with rest of RV
\item Extending RVV requires customisation not just of h/w:\\
gcc, binutils also need customisation (and maintenance)
- \item Fascinatingly, despite being a SIMD-variant, RVV only has
- O(N) opcode proliferation! (extremely well designed)
\end{itemize}
}
\item Standard and future and custom opcodes now parallel\\
(crucially: with NO extra instructions needing to be added)
\end{itemize}
- Note: EVERYTHING is parallelised:
+ Note: EVERY scalar op now paralleliseable
\begin{itemize}
\item All LOAD/STORE (inc. Compressed, Int/FP versions)
\item All ALU ops (Int, FP, SIMD, DSP, everything)