add clarification

[libreriscv.git] / simple_v_extension / simple_v_chennai_2018.tex

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 9b0207ecd02fa9bb5a7bad0d51560f1154e2c56b..bc69edf9e3f844042cfc8e5b62cc6452f8e500bf 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -50,7 +50,7 @@
    https://sigarch.org/simd-instructions-considered-harmful
    \item Setup and corner-cases alone are extremely complex.\\
             Hardware is easy, but software is hell.
-   \item O($N^{6}$) ISA opcode proliferation!\\
+   \item O($N^{6}$) ISA opcode proliferation (1000s of instructions)\\
             opcode, elwidth, veclen, src1-src2-dest hi/lo
   \end{itemize}
 }
@@ -150,7 +150,7 @@
    \item Standard and future and custom opcodes now parallel\\
          (crucially: with NO extra instructions needing to be added)
   \end{itemize}
-  Note: EVERYTHING is parallelised:
+  Note: EVERY scalar op now paralleliseable
    \begin{itemize}
    \item All LOAD/STORE (inc. Compressed, Int/FP versions)
    \item All ALU ops (Int, FP, SIMD, DSP, everything)