add images

[libreriscv.git] / simple_v_extension / simple_v_chennai_2018.tex

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index e83cd4c6bd24ada7151fedede927411d36aa4de3..bcc69b37c6a7a5f434d5ea24dd688ffa254596c9 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -485,17 +485,18 @@ for (int i = 0; i < VL; ++i)
 \frame{\frametitle{Summary}
 
  \begin{itemize}
-   \item Designed for flexibility (graded levels of complexity)\vspace{6pt}
-   \item Huge range of implementor freedom\vspace{6pt}
-   \item Fits RISC-V ethos: achieve more with less\vspace{6pt}
+   \item Actually about parallelism, not Vectors (or SIMD) per se
+   \item Designed for flexibility (graded levels of complexity)
+   \item Huge range of implementor freedom
+   \item Fits RISC-V ethos: achieve more with less
    \item Reduces SIMD ISA proliferation by 3-4 orders of magnitude \\
-            (without SIMD downsides or sacrificing speed trade-off)\vspace{6pt}
-   \item Covers 98\% of RVV, allows RVV to fit "on top"\vspace{6pt}
+            (without SIMD downsides or sacrificing speed trade-off)
+   \item Covers 98\% of RVV, allows RVV to fit "on top"
    \item Not designed for supercomputing (that's RVV), designed for
-         in between: DSPs, RV32E, Embedded 3D GPUs etc.\vspace{6pt}
+         in between: DSPs, RV32E, Embedded 3D GPUs etc.
    \item Not specifically designed for Vectorisation: designed to\\
             reduce code size (increase efficiency, just
-                like Compressed)\vspace{6pt}
+                like Compressed)
   \end{itemize}
 }