reorg

[libreriscv.git] / simple_v_extension / simple_v_chennai_2018.tex

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 22201be2d9ec0629c62ac6d46b61fd83f1783167..f39d023557dd1319345f06430964784a65772aa7 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -729,14 +729,6 @@ loop:
 }
 
 
-\frame{\frametitle{Is this OK (low latency)? Detect scalar-ops (only)}
- \begin{center}
-  \includegraphics[height=2.5in]{scalardetect.png}\\
-  {\bf \red Detect when all registers are scalar for a given op}
- \end{center}
-}
-
-
 \frame{\frametitle{Summary}
 
  \begin{itemize}