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[libreriscv.git] / simple_v_extension / specification.mdwn

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index dea2ffd36b9f8e33cee079ae00cbbba1f35d94e2..2b1160f8c58e6b3042a7b505a916321f26e6320f 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -1,3 +1,4 @@
+
 # Simple-V (Parallelism Extension Proposal) Specification
 
 * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton
@@ -9,8 +10,9 @@
 * Ancillary resource: [[vblock_format]]
 * Ancillary resource: [[appendix]]
 
-With thanks to:
+Authors/Contributors:
 
+* Luke Kenneth Casson Leighton
 * Allen Baum
 * Bruce Hoult
 * comp.arch
@@ -66,7 +68,7 @@ To emphasise that clearly: Simple-V (SV) is *not*:
 * A SIMT system
 * A Vectorisation Microarchitecture
 * A microarchitecture of any specific kind
-* A mandary parallel processor microarchitecture of any kind
+* A mandatory parallel processor microarchitecture of any kind
 * A supercomputer extension
 
 SV does **not** tell implementors how or even if they should implement