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[libreriscv.git] / simple_v_extension / specification.mdwn

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index fa86b961d8d40153e14663ba5771a31b0e088081..2b1160f8c58e6b3042a7b505a916321f26e6320f 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -1,4 +1,3 @@
-[[!tag standards]]
 
 # Simple-V (Parallelism Extension Proposal) Specification
 
@@ -11,8 +10,9 @@
 * Ancillary resource: [[vblock_format]]
 * Ancillary resource: [[appendix]]
 
-With thanks to:
+Authors/Contributors:
 
+* Luke Kenneth Casson Leighton
 * Allen Baum
 * Bruce Hoult
 * comp.arch
@@ -68,7 +68,7 @@ To emphasise that clearly: Simple-V (SV) is *not*:
 * A SIMT system
 * A Vectorisation Microarchitecture
 * A microarchitecture of any specific kind
-* A mandary parallel processor microarchitecture of any kind
+* A mandatory parallel processor microarchitecture of any kind
 * A supercomputer extension
 
 SV does **not** tell implementors how or even if they should implement