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[libreriscv.git] / simple_v_extension / sv_prefix_proposal.rst

diff --git a/simple_v_extension/sv_prefix_proposal.rst b/simple_v_extension/sv_prefix_proposal.rst
index ebf3f5ac154fff0c6f0d59f7c8fd579cef9056b0..9cfdd854164087ec888047631c6292d33320239c 100644 (file)
--- a/simple_v_extension/sv_prefix_proposal.rst
+++ b/simple_v_extension/sv_prefix_proposal.rst
@@ -1,3 +1,5 @@
+[[!tag oldstandards]]
+
 SimpleV Prefix (SVprefix) Proposal v0.3
 =======================================
 
@@ -12,6 +14,7 @@ into 32, 48 and 64 bit RV formats, to provide Vectorisation context
 on a per-instruction basis.
 
 .. _Specification: http://libre-riscv.org/simple_v_extension/specification/
+.. _Appendix: http://libre-riscv.org/simple_v_extension/appendix/
 
 .. contents::
 
@@ -434,6 +437,13 @@ Predication (pred) Field Encoding
 Twin-predication (tpred) Field Encoding
 =======================================
 
+Twin-predication (ability to associate two predicate registers with an
+instruction) applies to MV, FCLASS, LD and ST.  The same format also
+applies to integer-branch-compare operations although it is **not** to be
+considered "twin" predication.  In the case of integer-branch-compare
+operations, the second register (if enabled) stores the results of the
+element comparisons.  See Appendix_ for details.
+
 +-------+------------+--------------------+----------------------------------------------+
 | tpred | Mnemonic   | Predicate Register | Meaning                                      |
 +=======+============+====================+==============================================+