add (but comment out) reset signal

[ieee754fpu.git] / src / add / fpbase.py

diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index 7f4f2cc88d57813c22d70f31837290fcd2753e7e..aaf263e89dd95e5c3c1ff182fb21352a58825995 100644 (file)
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -398,7 +398,7 @@ class Trigger:
 
     def elaborate(self, platform):
         m = Module()
-        m.d.sync += self.trigger.eq(self.stb & self.ack)
+        m.d.comb += self.trigger.eq(self.stb & self.ack)
         return m
 
     def copy(self, inp):