identify test 9 code with comment

[ieee754fpu.git] / src / add / nmigen_add_experiment.py

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 30dcc711b8a4289990a99c9ba7a51e341b6eba9b..b7c771f7da989e8d4c4d9f66807c003622ee3905 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -9,7 +9,7 @@ from math import log
 
 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
 from fpbase import MultiShiftRMerge, Trigger
-from example_buf_pipe import StageChain
+from example_buf_pipe import StageChain, UnbufferedPipeline
 #from fpbase import FPNumShiftMultiRight
 
 
@@ -460,9 +460,9 @@ class FPAddSpecialCasesDeNorm(FPState):
         m.d.sync += self.o.eq(self.dmod.o)
 
     def action(self, m):
-        with m.If(self.out_do_z):
-            m.next = "put_z"
-        with m.Else():
+        #with m.If(self.out_do_z):
+        #    m.next = "put_z"
+        #with m.Else():
             m.next = "align"
 
 
@@ -840,9 +840,8 @@ class FPAddStage0Mod:
                     self.o.tot.eq(bm0 - am0),
                     self.o.z.s.eq(self.i.b.s)
             ]
-        with m.Else():
-            m.d.comb += self.o.oz.eq(self.i.z.v)
 
+        m.d.comb += self.o.oz.eq(self.i.oz)
         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
         m.d.comb += self.o.mid.eq(self.i.mid)
         return m
@@ -1721,8 +1720,8 @@ class FPADDBaseMod:
         ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
                                     n1.out_z.mid, self.o.mid))
 
-        pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
-                                    sc.o.mid, self.o.mid))
+        #pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
+        #                            sc.o.mid, self.o.mid))
 
 
 class FPADDBase(FPState):
@@ -1815,6 +1814,57 @@ class FPADDBase(FPState):
             with m.Else():
                 m.d.sync += self.out_z.stb.eq(1)
 
+class FPADDStageIn:
+    def __init__(self, width, id_wid):
+        self.a = Signal(width)
+        self.b = Signal(width)
+        self.mid = Signal(id_wid, reset_less=True)
+
+    def eq(self, i):
+        return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+
+
+class FPADDStageOut:
+    def __init__(self, width, id_wid):
+        self.z = Signal(width)
+        self.mid = Signal(id_wid, reset_less=True)
+
+    def eq(self, i):
+        return [self.z.eq(i.z), self.mid.eq(i.mid)]
+
+
+# matches the format of FPADDStageOut, allows eq function to do assignments
+class PlaceHolder: pass
+
+
+class FPAddBaseStage:
+    def __init__(self, width, id_wid):
+        self.width = width
+        self.id_wid = id_wid
+
+    def ispec(self):
+        return FPADDStageIn(self.width, self.id_wid)
+
+    def ospec(self):
+        return FPADDStageOut(self.width, self.id_wid)
+
+    def process(self, i):
+        o = PlaceHolder()
+        o.z = i.a + i.b
+        o.mid = i.mid
+        return o
+
+
+class FPADDBasePipe:
+    def __init__(self, width, id_wid):
+        stage1 = FPAddBaseStage(width, id_wid)
+        self.pipe = UnbufferedPipeline(stage1)
+
+    def elaborate(self, platform):
+        return self.pipe.elaborate(platform)
+
+    def ports(self):
+        return self.pipe.ports()
 
 class ResArray:
     def __init__(self, width, id_wid):