from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
from fpbase import MultiShiftRMerge, Trigger
-from example_buf_pipe import StageChain
+from example_buf_pipe import StageChain, UnbufferedPipeline
#from fpbase import FPNumShiftMultiRight
class FPSCData:
def __init__(self, width, id_wid):
- self.out_do_z = Signal(reset_less=True)
self.a = FPNumBase(width, True)
self.b = FPNumBase(width, True)
self.z = FPNumOut(width, False)
+ self.oz = Signal(width, reset_less=True)
+ self.out_do_z = Signal(reset_less=True)
self.mid = Signal(id_wid, reset_less=True)
def eq(self, i):
- return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z),
+ return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+
class FPAddSpecialCasesMod:
""" special cases: NaNs, infs, zeros, denormalised
NOTE: some of these are unique to add. see "Special Operations"
m.d.comb += self.o.out_do_z.eq(1)
m.d.comb += self.o.z.zero(0)
- # Denormalised Number checks
+ # Denormalised Number checks next, so pass a/b data through
with m.Else():
m.d.comb += self.o.out_do_z.eq(0)
+ m.d.comb += self.o.a.eq(self.i.a)
+ m.d.comb += self.o.b.eq(self.i.b)
+ m.d.comb += self.o.oz.eq(self.o.z.v)
m.d.comb += self.o.mid.eq(self.i.mid)
return m
""" links module to inputs and outputs
"""
self.smod.setup(m, i)
- self.dmod.setup(m, i)
+ self.dmod.setup(m, self.smod.o)
m.d.comb += self.out_do_z.eq(self.smod.o.out_do_z)
# out_do_z=True
m.d.sync += self.o.eq(self.dmod.o)
def action(self, m):
- with m.If(self.out_do_z):
- m.next = "put_z"
- with m.Else():
+ #with m.If(self.out_do_z):
+ # m.next = "put_z"
+ #with m.Else():
m.next = "align"
self.o = self.ospec()
def ispec(self):
- return FPNumBase2Ops(self.width, self.id_wid)
+ return FPSCData(self.width, self.id_wid)
def ospec(self):
- return FPNumBase2Ops(self.width, self.id_wid)
+ return FPSCData(self.width, self.id_wid)
def setup(self, m, i):
""" links module to inputs and outputs
m.submodules.denorm_in_b = self.i.b
m.submodules.denorm_out_a = self.o.a
m.submodules.denorm_out_b = self.o.b
- # hmmm, don't like repeating identical code
- m.d.comb += self.o.a.eq(self.i.a)
- with m.If(self.i.a.exp_n127):
- m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
- with m.Else():
- m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
- m.d.comb += self.o.b.eq(self.i.b)
- with m.If(self.i.b.exp_n127):
- m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
- with m.Else():
- m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
+ with m.If(~self.i.out_do_z):
+ # XXX hmmm, don't like repeating identical code
+ m.d.comb += self.o.a.eq(self.i.a)
+ with m.If(self.i.a.exp_n127):
+ m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
+ with m.Else():
+ m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
+
+ m.d.comb += self.o.b.eq(self.i.b)
+ with m.If(self.i.b.exp_n127):
+ m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
+ with m.Else():
+ m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
m.d.comb += self.o.mid.eq(self.i.mid)
+ m.d.comb += self.o.z.eq(self.i.z)
+ m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
+ m.d.comb += self.o.oz.eq(self.i.oz)
return m
def __init__(self, width, id_wid):
self.a = FPNumIn(None, width)
self.b = FPNumIn(None, width)
+ self.z = FPNumOut(width, False)
+ self.out_do_z = Signal(reset_less=True)
+ self.oz = Signal(width, reset_less=True)
self.mid = Signal(id_wid, reset_less=True)
def eq(self, i):
- return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+ return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+ self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
class FPAddAlignSingleMod:
self.o = self.ospec()
def ispec(self):
- return FPNumBase2Ops(self.width, self.id_wid)
+ return FPSCData(self.width, self.id_wid)
def ospec(self):
return FPNumIn2Ops(self.width, self.id_wid)
# only one shifter (muxed)
#m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
# exponent of a greater than b: shift b down
- with m.If(egz):
- m.d.comb += [t_inp.eq(self.i.b),
- tdiff.eq(ediff),
- self.o.b.eq(t_out),
- self.o.b.s.eq(self.i.b.s), # whoops forgot sign
- ]
- # exponent of b greater than a: shift a down
- with m.Elif(elz):
- m.d.comb += [t_inp.eq(self.i.a),
- tdiff.eq(ediffr),
- self.o.a.eq(t_out),
- self.o.a.s.eq(self.i.a.s), # whoops forgot sign
- ]
+ with m.If(~self.i.out_do_z):
+ with m.If(egz):
+ m.d.comb += [t_inp.eq(self.i.b),
+ tdiff.eq(ediff),
+ self.o.b.eq(t_out),
+ self.o.b.s.eq(self.i.b.s), # whoops forgot sign
+ ]
+ # exponent of b greater than a: shift a down
+ with m.Elif(elz):
+ m.d.comb += [t_inp.eq(self.i.a),
+ tdiff.eq(ediffr),
+ self.o.a.eq(t_out),
+ self.o.a.s.eq(self.i.a.s), # whoops forgot sign
+ ]
m.d.comb += self.o.mid.eq(self.i.mid)
+ m.d.comb += self.o.z.eq(self.i.z)
+ m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
+ m.d.comb += self.o.oz.eq(self.i.oz)
return m
def __init__(self, width, id_wid):
self.z = FPNumBase(width, False)
+ self.out_do_z = Signal(reset_less=True)
+ self.oz = Signal(width, reset_less=True)
self.tot = Signal(self.z.m_width + 4, reset_less=True)
self.mid = Signal(id_wid, reset_less=True)
def eq(self, i):
- return [self.z.eq(i.z), self.tot.eq(i.tot), self.mid.eq(i.mid)]
+ return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+ self.tot.eq(i.tot), self.mid.eq(i.mid)]
class FPAddStage0Mod:
self.o = self.ospec()
def ispec(self):
- return FPNumBase2Ops(self.width, self.id_wid)
+ return FPSCData(self.width, self.id_wid)
def ospec(self):
return FPAddStage0Data(self.width, self.id_wid)
m.submodules.add0_in_b = self.i.b
m.submodules.add0_out_z = self.o.z
- m.d.comb += self.o.mid.eq(self.i.mid)
- m.d.comb += self.o.z.e.eq(self.i.a.e)
-
# store intermediate tests (and zero-extended mantissas)
seq = Signal(reset_less=True)
mge = Signal(reset_less=True)
bm0.eq(Cat(self.i.b.m, 0))
]
# same-sign (both negative or both positive) add mantissas
- with m.If(seq):
- m.d.comb += [
- self.o.tot.eq(am0 + bm0),
- self.o.z.s.eq(self.i.a.s)
- ]
- # a mantissa greater than b, use a
- with m.Elif(mge):
- m.d.comb += [
- self.o.tot.eq(am0 - bm0),
- self.o.z.s.eq(self.i.a.s)
+ with m.If(~self.i.out_do_z):
+ m.d.comb += self.o.z.e.eq(self.i.a.e)
+ with m.If(seq):
+ m.d.comb += [
+ self.o.tot.eq(am0 + bm0),
+ self.o.z.s.eq(self.i.a.s)
+ ]
+ # a mantissa greater than b, use a
+ with m.Elif(mge):
+ m.d.comb += [
+ self.o.tot.eq(am0 - bm0),
+ self.o.z.s.eq(self.i.a.s)
+ ]
+ # b mantissa greater than a, use b
+ with m.Else():
+ m.d.comb += [
+ self.o.tot.eq(bm0 - am0),
+ self.o.z.s.eq(self.i.b.s)
]
- # b mantissa greater than a, use b
- with m.Else():
- m.d.comb += [
- self.o.tot.eq(bm0 - am0),
- self.o.z.s.eq(self.i.b.s)
- ]
+
+ m.d.comb += self.o.oz.eq(self.i.oz)
+ m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
+ m.d.comb += self.o.mid.eq(self.i.mid)
return m
def __init__(self, width, id_wid):
self.z = FPNumBase(width, False)
+ self.out_do_z = Signal(reset_less=True)
+ self.oz = Signal(width, reset_less=True)
self.of = Overflow()
self.mid = Signal(id_wid, reset_less=True)
def eq(self, i):
- return [self.z.eq(i.z), self.of.eq(i.of), self.mid.eq(i.mid)]
+ return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+ self.of.eq(i.of), self.mid.eq(i.mid)]
#m.submodules.norm1_in_z = self.in_z
#m.submodules.norm1_out_z = self.out_z
m.d.comb += self.o.z.eq(self.i.z)
- m.d.comb += self.o.mid.eq(self.i.mid)
# tot[-1] (MSB) gets set when the sum overflows. shift result down
- with m.If(self.i.tot[-1]):
- m.d.comb += [
- self.o.z.m.eq(self.i.tot[4:]),
- self.o.of.m0.eq(self.i.tot[4]),
- self.o.of.guard.eq(self.i.tot[3]),
- self.o.of.round_bit.eq(self.i.tot[2]),
- self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
- self.o.z.e.eq(self.i.z.e + 1)
- ]
- # tot[-1] (MSB) zero case
- with m.Else():
- m.d.comb += [
- self.o.z.m.eq(self.i.tot[3:]),
- self.o.of.m0.eq(self.i.tot[3]),
- self.o.of.guard.eq(self.i.tot[2]),
- self.o.of.round_bit.eq(self.i.tot[1]),
- self.o.of.sticky.eq(self.i.tot[0])
- ]
+ with m.If(~self.i.out_do_z):
+ with m.If(self.i.tot[-1]):
+ m.d.comb += [
+ self.o.z.m.eq(self.i.tot[4:]),
+ self.o.of.m0.eq(self.i.tot[4]),
+ self.o.of.guard.eq(self.i.tot[3]),
+ self.o.of.round_bit.eq(self.i.tot[2]),
+ self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
+ self.o.z.e.eq(self.i.z.e + 1)
+ ]
+ # tot[-1] (MSB) zero case
+ with m.Else():
+ m.d.comb += [
+ self.o.z.m.eq(self.i.tot[3:]),
+ self.o.of.m0.eq(self.i.tot[3]),
+ self.o.of.guard.eq(self.i.tot[2]),
+ self.o.of.round_bit.eq(self.i.tot[1]),
+ self.o.of.sticky.eq(self.i.tot[0])
+ ]
+
+ m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
+ m.d.comb += self.o.oz.eq(self.i.oz)
+ m.d.comb += self.o.mid.eq(self.i.mid)
+
return m
def __init__(self, width, id_wid):
self.roundz = Signal(reset_less=True)
self.z = FPNumBase(width, False)
+ self.out_do_z = Signal(reset_less=True)
+ self.oz = Signal(width, reset_less=True)
self.mid = Signal(id_wid, reset_less=True)
def eq(self, i):
- return [self.z.eq(i.z), self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
+ return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+ self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
class FPNorm1ModSingle:
m.d.comb += i.eq(self.i)
# initialise out from in (overridden below)
m.d.comb += self.o.z.eq(i.z)
- m.d.comb += self.o.mid.eq(self.i.mid)
m.d.comb += of.eq(i.of)
# normalisation increase/decrease conditions
decrease = Signal(reset_less=True)
m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
m.d.comb += increase.eq(i.z.exp_lt_n126)
# decrease exponent
- with m.If(decrease):
- # *sigh* not entirely obvious: count leading zeros (clz)
- # with a PriorityEncoder: to find from the MSB
- # we reverse the order of the bits.
- temp_m = Signal(mwid, reset_less=True)
- temp_s = Signal(mwid+1, reset_less=True)
- clz = Signal((len(i.z.e), True), reset_less=True)
- # make sure that the amount to decrease by does NOT
- # go below the minimum non-INF/NaN exponent
- limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
- i.z.exp_sub_n126)
- m.d.comb += [
- # cat round and guard bits back into the mantissa
- temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
- pe.i.eq(temp_m[::-1]), # inverted
- clz.eq(limclz), # count zeros from MSB down
- temp_s.eq(temp_m << clz), # shift mantissa UP
- self.o.z.e.eq(i.z.e - clz), # DECREASE exponent
- self.o.z.m.eq(temp_s[2:]), # exclude bits 0&1
- of.m0.eq(temp_s[2]), # copy of mantissa[0]
- # overflow in bits 0..1: got shifted too (leave sticky)
- of.guard.eq(temp_s[1]), # guard
- of.round_bit.eq(temp_s[0]), # round
- ]
- # increase exponent
- with m.Elif(increase):
- temp_m = Signal(mwid+1, reset_less=True)
- m.d.comb += [
- temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
- i.z.m)),
- ediff_n126.eq(i.z.N126 - i.z.e),
- # connect multi-shifter to inp/out mantissa (and ediff)
- msr.inp.eq(temp_m),
- msr.diff.eq(ediff_n126),
- self.o.z.m.eq(msr.m[3:]),
- of.m0.eq(temp_s[3]), # copy of mantissa[0]
- # overflow in bits 0..1: got shifted too (leave sticky)
- of.guard.eq(temp_s[2]), # guard
- of.round_bit.eq(temp_s[1]), # round
- of.sticky.eq(temp_s[0]), # sticky
- self.o.z.e.eq(i.z.e + ediff_n126),
- ]
+ with m.If(~self.i.out_do_z):
+ with m.If(decrease):
+ # *sigh* not entirely obvious: count leading zeros (clz)
+ # with a PriorityEncoder: to find from the MSB
+ # we reverse the order of the bits.
+ temp_m = Signal(mwid, reset_less=True)
+ temp_s = Signal(mwid+1, reset_less=True)
+ clz = Signal((len(i.z.e), True), reset_less=True)
+ # make sure that the amount to decrease by does NOT
+ # go below the minimum non-INF/NaN exponent
+ limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
+ i.z.exp_sub_n126)
+ m.d.comb += [
+ # cat round and guard bits back into the mantissa
+ temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
+ pe.i.eq(temp_m[::-1]), # inverted
+ clz.eq(limclz), # count zeros from MSB down
+ temp_s.eq(temp_m << clz), # shift mantissa UP
+ self.o.z.e.eq(i.z.e - clz), # DECREASE exponent
+ self.o.z.m.eq(temp_s[2:]), # exclude bits 0&1
+ of.m0.eq(temp_s[2]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ of.guard.eq(temp_s[1]), # guard
+ of.round_bit.eq(temp_s[0]), # round
+ ]
+ # increase exponent
+ with m.Elif(increase):
+ temp_m = Signal(mwid+1, reset_less=True)
+ m.d.comb += [
+ temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
+ i.z.m)),
+ ediff_n126.eq(i.z.N126 - i.z.e),
+ # connect multi-shifter to inp/out mantissa (and ediff)
+ msr.inp.eq(temp_m),
+ msr.diff.eq(ediff_n126),
+ self.o.z.m.eq(msr.m[3:]),
+ of.m0.eq(temp_s[3]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ of.guard.eq(temp_s[2]), # guard
+ of.round_bit.eq(temp_s[1]), # round
+ of.sticky.eq(temp_s[0]), # sticky
+ self.o.z.e.eq(i.z.e + ediff_n126),
+ ]
+
+ m.d.comb += self.o.mid.eq(self.i.mid)
+ m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
+ m.d.comb += self.o.oz.eq(self.i.oz)
return m
def __init__(self, width, id_wid):
self.z = FPNumBase(width, False)
+ self.out_do_z = Signal(reset_less=True)
+ self.oz = Signal(width, reset_less=True)
self.mid = Signal(id_wid, reset_less=True)
def eq(self, i):
- return [self.z.eq(i.z), self.mid.eq(i.mid)]
+ return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+ self.mid.eq(i.mid)]
class FPRoundMod:
def elaborate(self, platform):
m = Module()
- m.d.comb += self.out_z.eq(self.i)
- with m.If(self.i.roundz):
- m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa rounds up
- with m.If(self.i.z.m == self.i.z.m1s): # all 1s
- m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
+ m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
+ with m.If(~self.i.out_do_z):
+ with m.If(self.i.roundz):
+ m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa up
+ with m.If(self.i.z.m == self.i.z.m1s): # all 1s
+ m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
+
return m
m = Module()
m.submodules.corr_in_z = self.i.z
m.submodules.corr_out_z = self.out_z.z
- m.d.comb += self.out_z.eq(self.i)
- with m.If(self.i.z.is_denormalised):
- m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
+ m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
+ with m.If(~self.i.out_do_z):
+ with m.If(self.i.z.is_denormalised):
+ m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
return m
m = Module()
m.submodules.pack_in_z = self.i.z
m.d.comb += self.o.mid.eq(self.i.mid)
- with m.If(self.i.z.is_overflowed):
- m.d.comb += self.o.z.inf(self.i.z.s)
+ with m.If(~self.i.out_do_z):
+ with m.If(self.i.z.is_overflowed):
+ m.d.comb += self.o.z.inf(self.i.z.s)
+ with m.Else():
+ m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
with m.Else():
- m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
+ m.d.comb += self.o.z.v.eq(self.i.oz)
return m
-class FPPackData:
- def __init__(self, width, id_wid):
- self.z = FPNumOut(width, False)
- self.mid = Signal(id_wid, reset_less=True)
-
- def eq(self, i):
- return [self.z.eq(i.z), self.mid.eq(i.mid)]
-
-
class FPPack(FPState):
def __init__(self, width, id_wid):
ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
n1.out_z.mid, self.o.mid))
- pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
- sc.o.mid, self.o.mid))
+ #pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
+ # sc.o.mid, self.o.mid))
class FPADDBase(FPState):
with m.Else():
m.d.sync += self.out_z.stb.eq(1)
+class FPADDStageIn:
+ def __init__(self, width, id_wid):
+ self.a = Signal(width)
+ self.b = Signal(width)
+ self.mid = Signal(id_wid, reset_less=True)
+
+ def eq(self, i):
+ return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+
+
+class FPADDStageOut:
+ def __init__(self, width, id_wid):
+ self.z = Signal(width)
+ self.mid = Signal(id_wid, reset_less=True)
+
+ def eq(self, i):
+ return [self.z.eq(i.z), self.mid.eq(i.mid)]
+
+
+# matches the format of FPADDStageOut, allows eq function to do assignments
+class PlaceHolder: pass
+
+
+class FPAddBaseStage:
+ def __init__(self, width, id_wid):
+ self.width = width
+ self.id_wid = id_wid
+
+ def ispec(self):
+ return FPADDStageIn(self.width, self.id_wid)
+
+ def ospec(self):
+ return FPADDStageOut(self.width, self.id_wid)
+
+ def process(self, i):
+ o = PlaceHolder()
+ o.z = i.a + i.b
+ o.mid = i.mid
+ return o
+
+
+class FPADDBasePipe:
+ def __init__(self, width, id_wid):
+ stage1 = FPAddBaseStage(width, id_wid)
+ self.pipe = UnbufferedPipeline(stage1)
+
+ def elaborate(self, platform):
+ return self.pipe.elaborate(platform)
+
+ def ports(self):
+ return self.pipe.ports()
class ResArray:
def __init__(self, width, id_wid):
projects / ieee754fpu.git / blobdiff