from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
from fpbase import MultiShiftRMerge, Trigger
+from example_buf_pipe import StageChain, UnbufferedPipeline
#from fpbase import FPNumShiftMultiRight
out_op2.decode(self.i.b),
self.o.a.eq(out_op1),
self.o.b.eq(out_op2),
+ self.o.mid.eq(self.i.mid)
]
return m
return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+class FPSCData:
+
+ def __init__(self, width, id_wid):
+ self.a = FPNumBase(width, True)
+ self.b = FPNumBase(width, True)
+ self.z = FPNumOut(width, False)
+ self.oz = Signal(width, reset_less=True)
+ self.out_do_z = Signal(reset_less=True)
+ self.mid = Signal(id_wid, reset_less=True)
+
+ def eq(self, i):
+ return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+ self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+
+
class FPAddSpecialCasesMod:
""" special cases: NaNs, infs, zeros, denormalised
NOTE: some of these are unique to add. see "Special Operations"
self.id_wid = id_wid
self.i = self.ispec()
self.o = self.ospec()
- self.out_do_z = Signal(reset_less=True)
def ispec(self):
return FPNumBase2Ops(self.width, self.id_wid)
def ospec(self):
- return FPPackData(self.width, self.id_wid)
+ return FPSCData(self.width, self.id_wid)
- def setup(self, m, i, out_do_z):
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
m.submodules.specialcases = self
m.d.comb += self.i.eq(i)
- m.d.comb += out_do_z.eq(self.out_do_z)
def elaborate(self, platform):
m = Module()
# if a is NaN or b is NaN return NaN
with m.If(self.i.a.is_nan | self.i.b.is_nan):
- m.d.comb += self.out_do_z.eq(1)
+ m.d.comb += self.o.out_do_z.eq(1)
m.d.comb += self.o.z.nan(0)
# XXX WEIRDNESS for FP16 non-canonical NaN handling
## if a is zero and b is NaN return -b
#with m.If(a.is_zero & (a.s==0) & b.is_nan):
- # m.d.comb += self.out_do_z.eq(1)
+ # m.d.comb += self.o.out_do_z.eq(1)
# m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
## if b is zero and a is NaN return -a
#with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
- # m.d.comb += self.out_do_z.eq(1)
+ # m.d.comb += self.o.out_do_z.eq(1)
# m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
## if a is -zero and b is NaN return -b
#with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
- # m.d.comb += self.out_do_z.eq(1)
+ # m.d.comb += self.o.out_do_z.eq(1)
# m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
## if b is -zero and a is NaN return -a
#with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
- # m.d.comb += self.out_do_z.eq(1)
+ # m.d.comb += self.o.out_do_z.eq(1)
# m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
# if a is inf return inf (or NaN)
with m.Elif(self.i.a.is_inf):
- m.d.comb += self.out_do_z.eq(1)
+ m.d.comb += self.o.out_do_z.eq(1)
m.d.comb += self.o.z.inf(self.i.a.s)
# if a is inf and signs don't match return NaN
with m.If(self.i.b.exp_128 & s_nomatch):
# if b is inf return inf
with m.Elif(self.i.b.is_inf):
- m.d.comb += self.out_do_z.eq(1)
+ m.d.comb += self.o.out_do_z.eq(1)
m.d.comb += self.o.z.inf(self.i.b.s)
# if a is zero and b zero return signed-a/b
with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
- m.d.comb += self.out_do_z.eq(1)
+ m.d.comb += self.o.out_do_z.eq(1)
m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
self.i.b.e,
self.i.b.m[3:-1])
# if a is zero return b
with m.Elif(self.i.a.is_zero):
- m.d.comb += self.out_do_z.eq(1)
+ m.d.comb += self.o.out_do_z.eq(1)
m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
self.i.b.m[3:-1])
# if b is zero return a
with m.Elif(self.i.b.is_zero):
- m.d.comb += self.out_do_z.eq(1)
+ m.d.comb += self.o.out_do_z.eq(1)
m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
self.i.a.m[3:-1])
# if a equal to -b return zero (+ve zero)
with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
- m.d.comb += self.out_do_z.eq(1)
+ m.d.comb += self.o.out_do_z.eq(1)
m.d.comb += self.o.z.zero(0)
- # Denormalised Number checks
+ # Denormalised Number checks next, so pass a/b data through
with m.Else():
- m.d.comb += self.out_do_z.eq(0)
+ m.d.comb += self.o.out_do_z.eq(0)
+ m.d.comb += self.o.a.eq(self.i.a)
+ m.d.comb += self.o.b.eq(self.i.b)
+
+ m.d.comb += self.o.oz.eq(self.o.z.v)
+ m.d.comb += self.o.mid.eq(self.i.mid)
return m
m.d.sync += self.out_mid.eq(self.in_mid)
-class FPAddSpecialCases(FPState, FPID):
+class FPAddSpecialCases(FPState):
""" special cases: NaNs, infs, zeros, denormalised
NOTE: some of these are unique to add. see "Special Operations"
https://steve.hollasch.net/cgindex/coding/ieeefloat.html
def __init__(self, width, id_wid):
FPState.__init__(self, "special_cases")
- FPID.__init__(self, id_wid)
self.mod = FPAddSpecialCasesMod(width)
self.out_z = self.mod.ospec()
self.out_do_z = Signal(reset_less=True)
- def setup(self, m, in_a, in_b, in_mid):
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
- self.mod.setup(m, in_a, in_b, self.out_do_z)
- if self.in_mid is not None:
- m.d.comb += self.in_mid.eq(in_mid)
+ self.mod.setup(m, i, self.out_do_z)
+ m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
+ m.d.sync += self.out_z.mid.eq(self.mod.o.mid) # (and mid)
def action(self, m):
self.idsync(m)
with m.If(self.out_do_z):
- m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
m.next = "put_z"
with m.Else():
m.next = "denormalise"
-class FPAddSpecialCasesDeNorm(FPState, FPID):
+class FPAddSpecialCasesDeNorm(FPState):
""" special cases: NaNs, infs, zeros, denormalised
NOTE: some of these are unique to add. see "Special Operations"
https://steve.hollasch.net/cgindex/coding/ieeefloat.html
def __init__(self, width, id_wid):
FPState.__init__(self, "special_cases")
- FPID.__init__(self, id_wid)
self.smod = FPAddSpecialCasesMod(width, id_wid)
self.out_z = self.smod.ospec()
self.out_do_z = Signal(reset_less=True)
self.dmod = FPAddDeNormMod(width, id_wid)
self.o = self.dmod.ospec()
- def setup(self, m, i, in_mid):
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
- self.smod.setup(m, i, self.out_do_z)
- self.dmod.setup(m, i)
- if self.in_mid is not None:
- m.d.comb += self.in_mid.eq(in_mid)
+ self.smod.setup(m, i)
+ self.dmod.setup(m, self.smod.o)
+ m.d.comb += self.out_do_z.eq(self.smod.o.out_do_z)
+
+ # out_do_z=True
+ m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
+ m.d.sync += self.out_z.mid.eq(self.smod.o.mid) # (and mid)
+ # out_do_z=False
+ m.d.sync += self.o.eq(self.dmod.o)
def action(self, m):
- self.idsync(m)
- with m.If(self.out_do_z):
- m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
- m.next = "put_z"
- with m.Else():
+ #with m.If(self.out_do_z):
+ # m.next = "put_z"
+ #with m.Else():
m.next = "align"
- m.d.sync += self.o.a.eq(self.dmod.o.a)
- m.d.sync += self.o.b.eq(self.dmod.o.b)
class FPAddDeNormMod(FPState):
self.o = self.ospec()
def ispec(self):
- return FPNumBase2Ops(self.width, self.id_wid)
+ return FPSCData(self.width, self.id_wid)
def ospec(self):
- return FPNumBase2Ops(self.width, self.id_wid)
+ return FPSCData(self.width, self.id_wid)
def setup(self, m, i):
""" links module to inputs and outputs
m.submodules.denorm_in_b = self.i.b
m.submodules.denorm_out_a = self.o.a
m.submodules.denorm_out_b = self.o.b
- # hmmm, don't like repeating identical code
- m.d.comb += self.o.a.eq(self.i.a)
- with m.If(self.i.a.exp_n127):
- m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
- with m.Else():
- m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
- m.d.comb += self.o.b.eq(self.i.b)
- with m.If(self.i.b.exp_n127):
- m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
- with m.Else():
- m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
+ with m.If(~self.i.out_do_z):
+ # XXX hmmm, don't like repeating identical code
+ m.d.comb += self.o.a.eq(self.i.a)
+ with m.If(self.i.a.exp_n127):
+ m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
+ with m.Else():
+ m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
+
+ m.d.comb += self.o.b.eq(self.i.b)
+ with m.If(self.i.b.exp_n127):
+ m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
+ with m.Else():
+ m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
+
+ m.d.comb += self.o.mid.eq(self.i.mid)
+ m.d.comb += self.o.z.eq(self.i.z)
+ m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
+ m.d.comb += self.o.oz.eq(self.i.oz)
return m
-class FPAddDeNorm(FPState, FPID):
+class FPAddDeNorm(FPState):
def __init__(self, width, id_wid):
FPState.__init__(self, "denormalise")
- FPID.__init__(self, id_wid)
self.mod = FPAddDeNormMod(width)
self.out_a = FPNumBase(width)
self.out_b = FPNumBase(width)
- def setup(self, m, in_a, in_b, in_mid):
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
- self.mod.setup(m, in_a, in_b)
- if self.in_mid is not None:
- m.d.comb += self.in_mid.eq(in_mid)
+ self.mod.setup(m, i)
+
+ m.d.sync += self.out_a.eq(self.mod.out_a)
+ m.d.sync += self.out_b.eq(self.mod.out_b)
def action(self, m):
- self.idsync(m)
# Denormalised Number checks
m.next = "align"
- m.d.sync += self.out_a.eq(self.mod.out_a)
- m.d.sync += self.out_b.eq(self.mod.out_b)
class FPAddAlignMultiMod(FPState):
return m
-class FPAddAlignMulti(FPState, FPID):
+class FPAddAlignMulti(FPState):
def __init__(self, width, id_wid):
- FPID.__init__(self, id_wid)
FPState.__init__(self, "align")
self.mod = FPAddAlignMultiMod(width)
self.out_a = FPNumIn(None, width)
self.out_b = FPNumIn(None, width)
self.exp_eq = Signal(reset_less=True)
- def setup(self, m, in_a, in_b, in_mid):
+ def setup(self, m, in_a, in_b):
""" links module to inputs and outputs
"""
m.submodules.align = self.mod
#m.d.comb += self.out_a.eq(self.mod.out_a)
#m.d.comb += self.out_b.eq(self.mod.out_b)
m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
- if self.in_mid is not None:
- m.d.comb += self.in_mid.eq(in_mid)
-
- def action(self, m):
- self.idsync(m)
m.d.sync += self.out_a.eq(self.mod.out_a)
m.d.sync += self.out_b.eq(self.mod.out_b)
+
+ def action(self, m):
with m.If(self.exp_eq):
m.next = "add_0"
def __init__(self, width, id_wid):
self.a = FPNumIn(None, width)
self.b = FPNumIn(None, width)
+ self.z = FPNumOut(width, False)
+ self.out_do_z = Signal(reset_less=True)
+ self.oz = Signal(width, reset_less=True)
self.mid = Signal(id_wid, reset_less=True)
def eq(self, i):
- return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+ return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+ self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
class FPAddAlignSingleMod:
self.o = self.ospec()
def ispec(self):
- return FPNumBase2Ops(self.width, self.id_wid)
+ return FPSCData(self.width, self.id_wid)
def ospec(self):
return FPNumIn2Ops(self.width, self.id_wid)
+ def process(self, i):
+ return self.o
+
def setup(self, m, i):
""" links module to inputs and outputs
"""
# only one shifter (muxed)
#m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
# exponent of a greater than b: shift b down
- with m.If(egz):
- m.d.comb += [t_inp.eq(self.i.b),
- tdiff.eq(ediff),
- self.o.b.eq(t_out),
- self.o.b.s.eq(self.i.b.s), # whoops forgot sign
- ]
- # exponent of b greater than a: shift a down
- with m.Elif(elz):
- m.d.comb += [t_inp.eq(self.i.a),
- tdiff.eq(ediffr),
- self.o.a.eq(t_out),
- self.o.a.s.eq(self.i.a.s), # whoops forgot sign
- ]
+ with m.If(~self.i.out_do_z):
+ with m.If(egz):
+ m.d.comb += [t_inp.eq(self.i.b),
+ tdiff.eq(ediff),
+ self.o.b.eq(t_out),
+ self.o.b.s.eq(self.i.b.s), # whoops forgot sign
+ ]
+ # exponent of b greater than a: shift a down
+ with m.Elif(elz):
+ m.d.comb += [t_inp.eq(self.i.a),
+ tdiff.eq(ediffr),
+ self.o.a.eq(t_out),
+ self.o.a.s.eq(self.i.a.s), # whoops forgot sign
+ ]
+
+ m.d.comb += self.o.mid.eq(self.i.mid)
+ m.d.comb += self.o.z.eq(self.i.z)
+ m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
+ m.d.comb += self.o.oz.eq(self.i.oz)
+
return m
-class FPAddAlignSingle(FPState, FPID):
+class FPAddAlignSingle(FPState):
def __init__(self, width, id_wid):
FPState.__init__(self, "align")
- FPID.__init__(self, id_wid)
self.mod = FPAddAlignSingleMod(width, id_wid)
self.out_a = FPNumIn(None, width)
self.out_b = FPNumIn(None, width)
- def setup(self, m, in_a, in_b, in_mid):
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
- self.mod.setup(m, in_a, in_b)
- if self.in_mid is not None:
- m.d.comb += self.in_mid.eq(in_mid)
+ self.mod.setup(m, i)
- def action(self, m):
- self.idsync(m)
# NOTE: could be done as comb
m.d.sync += self.out_a.eq(self.mod.out_a)
m.d.sync += self.out_b.eq(self.mod.out_b)
+
+ def action(self, m):
m.next = "add_0"
-class FPAddAlignSingleAdd(FPState, FPID):
+class FPAddAlignSingleAdd(FPState):
def __init__(self, width, id_wid):
FPState.__init__(self, "align")
- FPID.__init__(self, id_wid)
self.width = width
self.id_wid = id_wid
- self.mod = FPAddAlignSingleMod(width, id_wid)
- self.o = self.mod.ospec()
+ self.a1o = self.ospec()
+
+ def ispec(self):
+ return FPNumBase2Ops(self.width, self.id_wid) # AlignSingle ispec
- self.a1mod = FPAddStage1Mod(width, id_wid)
- self.a1o = self.a1mod.ospec()
+ def ospec(self):
+ return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
- def setup(self, m, i, in_mid):
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
- self.mod.setup(m, i)
- m.d.comb += self.o.eq(self.mod.o)
+ # chain AddAlignSingle, AddStage0 and AddStage1
+ mod = FPAddAlignSingleMod(self.width, self.id_wid)
a0mod = FPAddStage0Mod(self.width, self.id_wid)
- a0mod.setup(m, self.o)
- a0o = a0mod.ospec()
- m.d.comb += a0o.eq(a0mod.o)
+ a1mod = FPAddStage1Mod(self.width, self.id_wid)
- self.a1mod.setup(m, a0o)
+ chain = StageChain([mod, a0mod, a1mod])
+ chain.setup(m, i)
- if self.in_mid is not None:
- m.d.comb += self.in_mid.eq(in_mid)
+ m.d.sync += self.a1o.eq(a1mod.o)
def action(self, m):
- self.idsync(m)
- m.d.sync += self.a1o.eq(self.a1mod.o)
m.next = "normalise_1"
def __init__(self, width, id_wid):
self.z = FPNumBase(width, False)
+ self.out_do_z = Signal(reset_less=True)
+ self.oz = Signal(width, reset_less=True)
self.tot = Signal(self.z.m_width + 4, reset_less=True)
self.mid = Signal(id_wid, reset_less=True)
def eq(self, i):
- return [self.z.eq(i.z), self.tot.eq(i.tot), self.mid.eq(i.mid)]
+ return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+ self.tot.eq(i.tot), self.mid.eq(i.mid)]
class FPAddStage0Mod:
self.o = self.ospec()
def ispec(self):
- return FPNumBase2Ops(self.width, self.id_wid)
+ return FPSCData(self.width, self.id_wid)
def ospec(self):
return FPAddStage0Data(self.width, self.id_wid)
+ def process(self, i):
+ return self.o
+
def setup(self, m, i):
""" links module to inputs and outputs
"""
m.submodules.add0_in_b = self.i.b
m.submodules.add0_out_z = self.o.z
- m.d.comb += self.o.z.e.eq(self.i.a.e)
-
# store intermediate tests (and zero-extended mantissas)
seq = Signal(reset_less=True)
mge = Signal(reset_less=True)
bm0.eq(Cat(self.i.b.m, 0))
]
# same-sign (both negative or both positive) add mantissas
- with m.If(seq):
- m.d.comb += [
- self.o.tot.eq(am0 + bm0),
- self.o.z.s.eq(self.i.a.s)
- ]
- # a mantissa greater than b, use a
- with m.Elif(mge):
- m.d.comb += [
- self.o.tot.eq(am0 - bm0),
- self.o.z.s.eq(self.i.a.s)
+ with m.If(~self.i.out_do_z):
+ m.d.comb += self.o.z.e.eq(self.i.a.e)
+ with m.If(seq):
+ m.d.comb += [
+ self.o.tot.eq(am0 + bm0),
+ self.o.z.s.eq(self.i.a.s)
+ ]
+ # a mantissa greater than b, use a
+ with m.Elif(mge):
+ m.d.comb += [
+ self.o.tot.eq(am0 - bm0),
+ self.o.z.s.eq(self.i.a.s)
+ ]
+ # b mantissa greater than a, use b
+ with m.Else():
+ m.d.comb += [
+ self.o.tot.eq(bm0 - am0),
+ self.o.z.s.eq(self.i.b.s)
]
- # b mantissa greater than a, use b
- with m.Else():
- m.d.comb += [
- self.o.tot.eq(bm0 - am0),
- self.o.z.s.eq(self.i.b.s)
- ]
+
+ m.d.comb += self.o.oz.eq(self.i.oz)
+ m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
+ m.d.comb += self.o.mid.eq(self.i.mid)
return m
-class FPAddStage0(FPState, FPID):
+class FPAddStage0(FPState):
""" First stage of add. covers same-sign (add) and subtract
special-casing when mantissas are greater or equal, to
give greatest accuracy.
def __init__(self, width, id_wid):
FPState.__init__(self, "add_0")
- FPID.__init__(self, id_wid)
self.mod = FPAddStage0Mod(width)
self.o = self.mod.ospec()
- def setup(self, m, i, in_mid):
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
self.mod.setup(m, i)
- if self.in_mid is not None:
- m.d.comb += self.in_mid.eq(in_mid)
- def action(self, m):
- self.idsync(m)
# NOTE: these could be done as combinatorial (merge add0+add1)
m.d.sync += self.o.eq(self.mod.o)
+
+ def action(self, m):
m.next = "add_1"
def __init__(self, width, id_wid):
self.z = FPNumBase(width, False)
+ self.out_do_z = Signal(reset_less=True)
+ self.oz = Signal(width, reset_less=True)
self.of = Overflow()
self.mid = Signal(id_wid, reset_less=True)
def eq(self, i):
- return [self.z.eq(i.z), self.of.eq(i.of), self.mid.eq(i.mid)]
+ return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+ self.of.eq(i.of), self.mid.eq(i.mid)]
def ospec(self):
return FPAddStage1Data(self.width, self.id_wid)
+ def process(self, i):
+ return self.o
+
def setup(self, m, i):
""" links module to inputs and outputs
"""
#m.submodules.norm1_out_z = self.out_z
m.d.comb += self.o.z.eq(self.i.z)
# tot[-1] (MSB) gets set when the sum overflows. shift result down
- with m.If(self.i.tot[-1]):
- m.d.comb += [
- self.o.z.m.eq(self.i.tot[4:]),
- self.o.of.m0.eq(self.i.tot[4]),
- self.o.of.guard.eq(self.i.tot[3]),
- self.o.of.round_bit.eq(self.i.tot[2]),
- self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
- self.o.z.e.eq(self.i.z.e + 1)
- ]
- # tot[-1] (MSB) zero case
- with m.Else():
- m.d.comb += [
- self.o.z.m.eq(self.i.tot[3:]),
- self.o.of.m0.eq(self.i.tot[3]),
- self.o.of.guard.eq(self.i.tot[2]),
- self.o.of.round_bit.eq(self.i.tot[1]),
- self.o.of.sticky.eq(self.i.tot[0])
- ]
+ with m.If(~self.i.out_do_z):
+ with m.If(self.i.tot[-1]):
+ m.d.comb += [
+ self.o.z.m.eq(self.i.tot[4:]),
+ self.o.of.m0.eq(self.i.tot[4]),
+ self.o.of.guard.eq(self.i.tot[3]),
+ self.o.of.round_bit.eq(self.i.tot[2]),
+ self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
+ self.o.z.e.eq(self.i.z.e + 1)
+ ]
+ # tot[-1] (MSB) zero case
+ with m.Else():
+ m.d.comb += [
+ self.o.z.m.eq(self.i.tot[3:]),
+ self.o.of.m0.eq(self.i.tot[3]),
+ self.o.of.guard.eq(self.i.tot[2]),
+ self.o.of.round_bit.eq(self.i.tot[1]),
+ self.o.of.sticky.eq(self.i.tot[0])
+ ]
+
+ m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
+ m.d.comb += self.o.oz.eq(self.i.oz)
+ m.d.comb += self.o.mid.eq(self.i.mid)
+
return m
-class FPAddStage1(FPState, FPID):
+class FPAddStage1(FPState):
def __init__(self, width, id_wid):
FPState.__init__(self, "add_1")
- FPID.__init__(self, id_wid)
self.mod = FPAddStage1Mod(width)
self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
self.norm_stb = Signal()
- def setup(self, m, i, in_mid):
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
self.mod.setup(m, i)
m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
- if self.in_mid is not None:
- m.d.comb += self.in_mid.eq(in_mid)
-
- def action(self, m):
- self.idsync(m)
m.d.sync += self.out_of.eq(self.mod.out_of)
m.d.sync += self.out_z.eq(self.mod.out_z)
m.d.sync += self.norm_stb.eq(1)
+
+ def action(self, m):
m.next = "normalise_1"
def __init__(self, width, id_wid):
self.roundz = Signal(reset_less=True)
self.z = FPNumBase(width, False)
+ self.out_do_z = Signal(reset_less=True)
+ self.oz = Signal(width, reset_less=True)
self.mid = Signal(id_wid, reset_less=True)
def eq(self, i):
- return [self.z.eq(i.z), self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
+ return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+ self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
class FPNorm1ModSingle:
m.submodules.normalise_1 = self
m.d.comb += self.i.eq(i)
+ def process(self, i):
+ return self.o
+
def elaborate(self, platform):
m = Module()
m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
m.d.comb += increase.eq(i.z.exp_lt_n126)
# decrease exponent
- with m.If(decrease):
- # *sigh* not entirely obvious: count leading zeros (clz)
- # with a PriorityEncoder: to find from the MSB
- # we reverse the order of the bits.
- temp_m = Signal(mwid, reset_less=True)
- temp_s = Signal(mwid+1, reset_less=True)
- clz = Signal((len(i.z.e), True), reset_less=True)
- # make sure that the amount to decrease by does NOT
- # go below the minimum non-INF/NaN exponent
- limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
- i.z.exp_sub_n126)
- m.d.comb += [
- # cat round and guard bits back into the mantissa
- temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
- pe.i.eq(temp_m[::-1]), # inverted
- clz.eq(limclz), # count zeros from MSB down
- temp_s.eq(temp_m << clz), # shift mantissa UP
- self.o.z.e.eq(i.z.e - clz), # DECREASE exponent
- self.o.z.m.eq(temp_s[2:]), # exclude bits 0&1
- of.m0.eq(temp_s[2]), # copy of mantissa[0]
- # overflow in bits 0..1: got shifted too (leave sticky)
- of.guard.eq(temp_s[1]), # guard
- of.round_bit.eq(temp_s[0]), # round
- ]
- # increase exponent
- with m.Elif(increase):
- temp_m = Signal(mwid+1, reset_less=True)
- m.d.comb += [
- temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
- i.z.m)),
- ediff_n126.eq(i.z.N126 - i.z.e),
- # connect multi-shifter to inp/out mantissa (and ediff)
- msr.inp.eq(temp_m),
- msr.diff.eq(ediff_n126),
- self.o.z.m.eq(msr.m[3:]),
- of.m0.eq(temp_s[3]), # copy of mantissa[0]
- # overflow in bits 0..1: got shifted too (leave sticky)
- of.guard.eq(temp_s[2]), # guard
- of.round_bit.eq(temp_s[1]), # round
- of.sticky.eq(temp_s[0]), # sticky
- self.o.z.e.eq(i.z.e + ediff_n126),
- ]
+ with m.If(~self.i.out_do_z):
+ with m.If(decrease):
+ # *sigh* not entirely obvious: count leading zeros (clz)
+ # with a PriorityEncoder: to find from the MSB
+ # we reverse the order of the bits.
+ temp_m = Signal(mwid, reset_less=True)
+ temp_s = Signal(mwid+1, reset_less=True)
+ clz = Signal((len(i.z.e), True), reset_less=True)
+ # make sure that the amount to decrease by does NOT
+ # go below the minimum non-INF/NaN exponent
+ limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
+ i.z.exp_sub_n126)
+ m.d.comb += [
+ # cat round and guard bits back into the mantissa
+ temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
+ pe.i.eq(temp_m[::-1]), # inverted
+ clz.eq(limclz), # count zeros from MSB down
+ temp_s.eq(temp_m << clz), # shift mantissa UP
+ self.o.z.e.eq(i.z.e - clz), # DECREASE exponent
+ self.o.z.m.eq(temp_s[2:]), # exclude bits 0&1
+ of.m0.eq(temp_s[2]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ of.guard.eq(temp_s[1]), # guard
+ of.round_bit.eq(temp_s[0]), # round
+ ]
+ # increase exponent
+ with m.Elif(increase):
+ temp_m = Signal(mwid+1, reset_less=True)
+ m.d.comb += [
+ temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
+ i.z.m)),
+ ediff_n126.eq(i.z.N126 - i.z.e),
+ # connect multi-shifter to inp/out mantissa (and ediff)
+ msr.inp.eq(temp_m),
+ msr.diff.eq(ediff_n126),
+ self.o.z.m.eq(msr.m[3:]),
+ of.m0.eq(temp_s[3]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ of.guard.eq(temp_s[2]), # guard
+ of.round_bit.eq(temp_s[1]), # round
+ of.sticky.eq(temp_s[0]), # sticky
+ self.o.z.e.eq(i.z.e + ediff_n126),
+ ]
+
+ m.d.comb += self.o.mid.eq(self.i.mid)
+ m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
+ m.d.comb += self.o.oz.eq(self.i.oz)
return m
return m
-class FPNorm1Single(FPState, FPID):
+class FPNorm1Single(FPState):
def __init__(self, width, id_wid, single_cycle=True):
- FPID.__init__(self, id_wid)
FPState.__init__(self, "normalise_1")
self.mod = FPNorm1ModSingle(width)
+ self.o = self.ospec()
self.out_z = FPNumBase(width, False)
self.out_roundz = Signal(reset_less=True)
- def setup(self, m, i, in_mid):
+ def ispec(self):
+ return self.mod.ispec()
+
+ def ospec(self):
+ return self.mod.ospec()
+
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
- self.mod.setup(m, i, self.out_z)
-
- if self.in_mid is not None:
- m.d.comb += self.in_mid.eq(in_mid)
+ self.mod.setup(m, i)
def action(self, m):
- self.idsync(m)
- m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
m.next = "round"
-class FPNorm1Multi(FPState, FPID):
+class FPNorm1Multi(FPState):
def __init__(self, width, id_wid):
- FPID.__init__(self, id_wid)
FPState.__init__(self, "normalise_1")
self.mod = FPNorm1ModMulti(width)
self.stb = Signal(reset_less=True)
self.out_z = FPNumBase(width)
self.out_roundz = Signal(reset_less=True)
- def setup(self, m, in_z, in_of, norm_stb, in_mid):
+ def setup(self, m, in_z, in_of, norm_stb):
""" links module to inputs and outputs
"""
self.mod.setup(m, in_z, in_of, norm_stb,
m.d.comb += self.stb.eq(norm_stb)
m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
- if self.in_mid is not None:
- m.d.comb += self.in_mid.eq(in_mid)
-
def action(self, m):
- self.idsync(m)
m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
m.d.sync += self.temp_of.eq(self.mod.out_of)
m.d.sync += self.temp_z.eq(self.out_z)
m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
-class FPNormToPack(FPState, FPID):
+class FPNormToPack(FPState):
def __init__(self, width, id_wid):
- FPID.__init__(self, id_wid)
FPState.__init__(self, "normalise_1")
+ self.id_wid = id_wid
self.width = width
- def setup(self, m, i, in_mid):
+ def ispec(self):
+ return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec
+
+ def ospec(self):
+ return FPPackData(self.width, self.id_wid) # FPPackMod ospec
+
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
- # Normalisation (chained to input in_z+in_of)
+ # Normalisation, Rounding Corrections, Pack - in a chain
nmod = FPNorm1ModSingle(self.width, self.id_wid)
- nmod.setup(m, i)
- n_out = nmod.ospec()
- m.d.comb += n_out.eq(nmod.o)
-
- # Rounding (chained to normalisation)
rmod = FPRoundMod(self.width, self.id_wid)
- rmod.setup(m, n_out)
- r_out_z = rmod.ospec()
- m.d.comb += r_out_z.eq(rmod.out_z)
-
- # Corrections (chained to rounding)
cmod = FPCorrectionsMod(self.width, self.id_wid)
- cmod.setup(m, r_out_z)
- c_out_z = cmod.ospec()
- m.d.comb += c_out_z.eq(cmod.out_z)
-
- # Pack (chained to corrections)
- self.pmod = FPPackMod(self.width, self.id_wid)
- self.pmod.setup(m, c_out_z)
- self.out_z = self.pmod.ospec()
+ pmod = FPPackMod(self.width, self.id_wid)
+ chain = StageChain([nmod, rmod, cmod, pmod])
+ chain.setup(m, i)
+ self.out_z = pmod.ospec()
- # Multiplex ID
- if self.in_mid is not None:
- m.d.comb += self.in_mid.eq(in_mid)
+ m.d.sync += self.out_z.mid.eq(pmod.o.mid)
+ m.d.sync += self.out_z.z.v.eq(pmod.o.z.v) # outputs packed result
def action(self, m):
- self.idsync(m) # copies incoming ID to outgoing
- m.d.sync += self.out_z.z.v.eq(self.pmod.o.z.v) # outputs packed result
m.next = "pack_put_z"
def __init__(self, width, id_wid):
self.z = FPNumBase(width, False)
+ self.out_do_z = Signal(reset_less=True)
+ self.oz = Signal(width, reset_less=True)
self.mid = Signal(id_wid, reset_less=True)
def eq(self, i):
- return [self.z.eq(i.z), self.mid.eq(i.mid)]
+ return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+ self.mid.eq(i.mid)]
class FPRoundMod:
def ospec(self):
return FPRoundData(self.width, self.id_wid)
+ def process(self, i):
+ return self.out_z
+
def setup(self, m, i):
m.submodules.roundz = self
m.d.comb += self.i.eq(i)
def elaborate(self, platform):
m = Module()
- m.d.comb += self.out_z.eq(self.i)
- with m.If(self.i.roundz):
- m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa rounds up
- with m.If(self.i.z.m == self.i.z.m1s): # all 1s
- m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
+ m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
+ with m.If(~self.i.out_do_z):
+ with m.If(self.i.roundz):
+ m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa up
+ with m.If(self.i.z.m == self.i.z.m1s): # all 1s
+ m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
+
return m
-class FPRound(FPState, FPID):
+class FPRound(FPState):
def __init__(self, width, id_wid):
FPState.__init__(self, "round")
- FPID.__init__(self, id_wid)
self.mod = FPRoundMod(width)
- self.out_z = self.mod.ospec()
+ self.out_z = self.ospec()
- def setup(self, m, i, in_mid):
+ def ispec(self):
+ return self.mod.ispec()
+
+ def ospec(self):
+ return self.mod.ospec()
+
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
self.mod.setup(m, i)
- if self.in_mid is not None:
- m.d.comb += self.in_mid.eq(in_mid)
-
- def action(self, m):
self.idsync(m)
m.d.sync += self.out_z.eq(self.mod.out_z)
+ m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
+
+ def action(self, m):
m.next = "corrections"
def ospec(self):
return FPRoundData(self.width, self.id_wid)
+ def process(self, i):
+ return self.out_z
+
def setup(self, m, i):
""" links module to inputs and outputs
"""
m = Module()
m.submodules.corr_in_z = self.i.z
m.submodules.corr_out_z = self.out_z.z
- m.d.comb += self.out_z.eq(self.i)
- with m.If(self.i.z.is_denormalised):
- m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
+ m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
+ with m.If(~self.i.out_do_z):
+ with m.If(self.i.z.is_denormalised):
+ m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
return m
-class FPCorrections(FPState, FPID):
+class FPCorrections(FPState):
def __init__(self, width, id_wid):
FPState.__init__(self, "corrections")
- FPID.__init__(self, id_wid)
self.mod = FPCorrectionsMod(width)
self.out_z = self.ospec()
def ospec(self):
return self.mod.ospec()
- def setup(self, m, in_z, in_mid):
+ def setup(self, m, in_z):
""" links module to inputs and outputs
"""
self.mod.setup(m, in_z)
- if self.in_mid is not None:
- m.d.comb += self.in_mid.eq(in_mid)
- def action(self, m):
- self.idsync(m)
m.d.sync += self.out_z.eq(self.mod.out_z)
+ m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
+
+ def action(self, m):
m.next = "pack"
def ospec(self):
return FPPackData(self.width, self.id_wid)
+ def process(self, i):
+ return self.o
+
def setup(self, m, in_z):
""" links module to inputs and outputs
"""
def elaborate(self, platform):
m = Module()
m.submodules.pack_in_z = self.i.z
- with m.If(self.i.z.is_overflowed):
- m.d.comb += self.o.z.inf(self.i.z.s)
+ m.d.comb += self.o.mid.eq(self.i.mid)
+ with m.If(~self.i.out_do_z):
+ with m.If(self.i.z.is_overflowed):
+ m.d.comb += self.o.z.inf(self.i.z.s)
+ with m.Else():
+ m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
with m.Else():
- m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
+ m.d.comb += self.o.z.v.eq(self.i.oz)
return m
-class FPPackData:
- def __init__(self, width, id_wid):
- self.z = FPNumOut(width, False)
- self.mid = Signal(id_wid, reset_less=True)
-
- def eq(self, i):
- return [self.z.eq(i.z), self.mid.eq(i.mid)]
-
-
-class FPPack(FPState, FPID):
+class FPPack(FPState):
def __init__(self, width, id_wid):
FPState.__init__(self, "pack")
- FPID.__init__(self, id_wid)
self.mod = FPPackMod(width)
self.out_z = self.ospec()
def ospec(self):
return self.mod.ospec()
- def setup(self, m, in_z, in_mid):
+ def setup(self, m, in_z):
""" links module to inputs and outputs
"""
self.mod.setup(m, in_z)
- if self.in_mid is not None:
- m.d.comb += self.in_mid.eq(in_mid)
- def action(self, m):
- self.idsync(m)
m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
+ m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
+
+ def action(self, m):
m.next = "pack_put_z"
return [self.z.eq(i.z), self.mid.eq(i.mid)]
-class FPADDBaseMod(FPID):
+class FPADDBaseMod:
def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
""" IEEE754 FP Add
* single_cycle: True indicates each stage to complete in 1 clock
* compact: True indicates a reduced number of stages
"""
- FPID.__init__(self, id_wid)
self.width = width
self.id_wid = id_wid
self.single_cycle = single_cycle
get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
- sc.setup(m, get.o, self.in_mid)
+ sc.setup(m, get.o)
alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
- alm.setup(m, sc.o, sc.in_mid)
+ alm.setup(m, sc.o)
n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
- n1.setup(m, alm.a1o, alm.in_mid)
+ n1.setup(m, alm.a1o)
ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
- n1.in_mid, self.out_mid))
+ n1.out_z.mid, self.o.mid))
- pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
- sc.in_mid, self.out_mid))
+ #pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
+ # sc.o.mid, self.o.mid))
-class FPADDBase(FPState, FPID):
+class FPADDBase(FPState):
def __init__(self, width, id_wid=None, single_cycle=False):
""" IEEE754 FP Add
* id_wid: an identifier that is sync-connected to the input
* single_cycle: True indicates each stage to complete in 1 clock
"""
- FPID.__init__(self, id_wid)
FPState.__init__(self, "fpadd")
self.width = width
self.single_cycle = single_cycle
def setup(self, m, i, add_stb, in_mid):
m.d.comb += [self.i.eq(i),
self.mod.i.eq(self.i),
- self.in_mid.eq(in_mid),
- self.mod.in_mid.eq(self.in_mid),
self.z_done.eq(self.mod.o.z.trigger),
#self.add_stb.eq(add_stb),
self.mod.in_t.stb.eq(self.in_t.stb),
with m.Else():
m.d.sync += self.out_z.stb.eq(1)
+class FPADDStageIn:
+ def __init__(self, width, id_wid):
+ self.a = Signal(width)
+ self.b = Signal(width)
+ self.mid = Signal(id_wid, reset_less=True)
+
+ def eq(self, i):
+ return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+
+
+class FPADDStageOut:
+ def __init__(self, width, id_wid):
+ self.z = Signal(width)
+ self.mid = Signal(id_wid, reset_less=True)
+
+ def eq(self, i):
+ return [self.z.eq(i.z), self.mid.eq(i.mid)]
+
+
+# matches the format of FPADDStageOut, allows eq function to do assignments
+class PlaceHolder: pass
+
+
+class FPAddBaseStage:
+ def __init__(self, width, id_wid):
+ self.width = width
+ self.id_wid = id_wid
+
+ def ispec(self):
+ return FPADDStageIn(self.width, self.id_wid)
+
+ def ospec(self):
+ return FPADDStageOut(self.width, self.id_wid)
+
+ def process(self, i):
+ o = PlaceHolder()
+ o.z = i.a + i.b
+ o.mid = i.mid
+ return o
+
+
+class FPADDBasePipe:
+ def __init__(self, width, id_wid):
+ stage1 = FPAddBaseStage(width, id_wid)
+ self.pipe = UnbufferedPipeline(stage1)
+
+ def elaborate(self, platform):
+ return self.pipe.elaborate(platform)
+
+ def ports(self):
+ return self.pipe.ports()
class ResArray:
def __init__(self, width, id_wid):
projects / ieee754fpu.git / blobdiff