# Copyright (C) Jonathan P Dawson 2013
# 2013-12-12
-from nmigen import Module, Signal, Cat, Mux
+from nmigen import Module, Signal, Cat, Mux, Array, Const
from nmigen.lib.coding import PriorityEncoder
from nmigen.cli import main, verilog
+from math import log
from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
from fpbase import MultiShiftRMerge, Trigger
#from fpbase import FPNumShiftMultiRight
+
class FPState(FPBase):
def __init__(self, state_from):
self.state_from = state_from
setattr(self, k, v)
+class FPGetSyncOpsMod:
+ def __init__(self, width, num_ops=2):
+ self.width = width
+ self.num_ops = num_ops
+ inops = []
+ outops = []
+ for i in range(num_ops):
+ inops.append(Signal(width, reset_less=True))
+ outops.append(Signal(width, reset_less=True))
+ self.in_op = inops
+ self.out_op = outops
+ self.stb = Signal(num_ops)
+ self.ack = Signal()
+ self.ready = Signal(reset_less=True)
+ self.out_decode = Signal(reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
+ m.d.comb += self.out_decode.eq(self.ack & self.ready)
+ with m.If(self.out_decode):
+ for i in range(self.num_ops):
+ m.d.comb += [
+ self.out_op[i].eq(self.in_op[i]),
+ ]
+ return m
+
+ def ports(self):
+ return self.in_op + self.out_op + [self.stb, self.ack]
+
+
+class FPOps(Trigger):
+ def __init__(self, width, num_ops):
+ Trigger.__init__(self)
+ self.width = width
+ self.num_ops = num_ops
+
+ res = []
+ for i in range(num_ops):
+ res.append(Signal(width))
+ self.v = Array(res)
+
+ def ports(self):
+ res = []
+ for i in range(self.num_ops):
+ res.append(self.v[i])
+ res.append(self.ack)
+ res.append(self.stb)
+ return res
+
+
+class InputGroup:
+ def __init__(self, width, num_ops=2, num_rows=4):
+ self.width = width
+ self.num_ops = num_ops
+ self.num_rows = num_rows
+ self.mmax = int(log(self.num_rows) / log(2))
+ self.rs = []
+ self.mid = Signal(self.mmax, reset_less=True) # multiplex id
+ for i in range(num_rows):
+ self.rs.append(FPGetSyncOpsMod(width, num_ops))
+ self.rs = Array(self.rs)
+
+ self.out_op = FPOps(width, num_ops)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ pe = PriorityEncoder(self.num_rows)
+ m.submodules.selector = pe
+ m.submodules.out_op = self.out_op
+ m.submodules.out_op_v = self.out_op.v
+ m.submodules += self.rs
+
+ # connect priority encoder
+ in_ready = []
+ for i in range(self.num_rows):
+ in_ready.append(self.rs[i].ready)
+ m.d.comb += pe.i.eq(Cat(*in_ready))
+
+ active = Signal(reset_less=True)
+ out_en = Signal(reset_less=True)
+ m.d.comb += active.eq(~pe.n) # encoder active
+ m.d.comb += out_en.eq(active & self.out_op.trigger)
+
+ # encoder active: ack relevant input, record MID, pass output
+ with m.If(out_en):
+ rs = self.rs[pe.o]
+ m.d.sync += self.mid.eq(pe.o)
+ m.d.sync += rs.ack.eq(0)
+ m.d.sync += self.out_op.stb.eq(0)
+ for j in range(self.num_ops):
+ m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
+ with m.Else():
+ m.d.sync += self.out_op.stb.eq(1)
+ # acks all default to zero
+ for i in range(self.num_rows):
+ m.d.sync += self.rs[i].ack.eq(1)
+
+ return m
+
+ def ports(self):
+ res = []
+ for i in range(self.num_rows):
+ inop = self.rs[i]
+ res += inop.in_op + [inop.stb]
+ return self.out_op.ports() + res + [self.mid]
+
+
class FPGetOpMod:
def __init__(self, width):
self.in_op = FPOp(width)
self.out_z = FPNumOut(width, False)
self.out_do_z = Signal(reset_less=True)
+ def setup(self, m, in_a, in_b, out_do_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.specialcases = self
+ m.d.comb += self.in_a.copy(in_a)
+ m.d.comb += self.in_b.copy(in_b)
+ m.d.comb += out_do_z.eq(self.out_do_z)
+
def elaborate(self, platform):
m = Module()
def setup(self, m, in_a, in_b, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.specialcases = self.mod
- m.d.comb += self.mod.in_a.copy(in_a)
- m.d.comb += self.mod.in_b.copy(in_b)
- #m.d.comb += self.out_z.v.eq(self.mod.out_z.v)
- m.d.comb += self.out_do_z.eq(self.mod.out_do_z)
+ self.mod.setup(m, in_a, in_b, self.out_do_z)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
m.next = "denormalise"
+class FPAddSpecialCasesDeNorm(FPState, FPID):
+ """ special cases: NaNs, infs, zeros, denormalised
+ NOTE: some of these are unique to add. see "Special Operations"
+ https://steve.hollasch.net/cgindex/coding/ieeefloat.html
+ """
+
+ def __init__(self, width, id_wid):
+ FPState.__init__(self, "special_cases")
+ FPID.__init__(self, id_wid)
+ self.smod = FPAddSpecialCasesMod(width)
+ self.out_z = FPNumOut(width, False)
+ self.out_do_z = Signal(reset_less=True)
+
+ self.dmod = FPAddDeNormMod(width)
+ self.out_a = FPNumBase(width)
+ self.out_b = FPNumBase(width)
+
+ def setup(self, m, in_a, in_b, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.smod.setup(m, in_a, in_b, self.out_do_z)
+ self.dmod.setup(m, in_a, in_b)
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ with m.If(self.out_do_z):
+ m.d.sync += self.out_z.v.eq(self.smod.out_z.v) # only take output
+ m.next = "put_z"
+ with m.Else():
+ m.next = "align"
+ m.d.sync += self.out_a.copy(self.dmod.out_a)
+ m.d.sync += self.out_b.copy(self.dmod.out_b)
+
+
class FPAddDeNormMod(FPState):
def __init__(self, width):
self.out_a = FPNumBase(width)
self.out_b = FPNumBase(width)
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.denormalise = self
+ m.d.comb += self.in_a.copy(in_a)
+ m.d.comb += self.in_b.copy(in_b)
+
def elaborate(self, platform):
m = Module()
m.submodules.denorm_in_a = self.in_a
def setup(self, m, in_a, in_b, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.denormalise = self.mod
- m.d.comb += self.mod.in_a.copy(in_a)
- m.d.comb += self.mod.in_b.copy(in_b)
+ self.mod.setup(m, in_a, in_b)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
self.out_a = FPNumIn(None, width)
self.out_b = FPNumIn(None, width)
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.align = self
+ m.d.comb += self.in_a.copy(in_a)
+ m.d.comb += self.in_b.copy(in_b)
+
def elaborate(self, platform):
""" Aligns A against B or B against A, depending on which has the
greater exponent. This is done in a *single* cycle using
def setup(self, m, in_a, in_b, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.align = self.mod
- m.d.comb += self.mod.in_a.copy(in_a)
- m.d.comb += self.mod.in_b.copy(in_b)
+ self.mod.setup(m, in_a, in_b)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
m.next = "add_0"
+class FPAddAlignSingleAdd(FPState, FPID):
+
+ def __init__(self, width, id_wid):
+ FPState.__init__(self, "align")
+ FPID.__init__(self, id_wid)
+ self.mod = FPAddAlignSingleMod(width)
+ self.out_a = FPNumIn(None, width)
+ self.out_b = FPNumIn(None, width)
+
+ self.a0mod = FPAddStage0Mod(width)
+ self.a0_out_z = FPNumBase(width, False)
+ self.out_tot = Signal(self.a0_out_z.m_width + 4, reset_less=True)
+ self.a0_out_z = FPNumBase(width, False)
+
+ self.a1mod = FPAddStage1Mod(width)
+ self.out_z = FPNumBase(width, False)
+ self.out_of = Overflow()
+
+ def setup(self, m, in_a, in_b, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.mod.setup(m, in_a, in_b)
+ m.d.comb += self.out_a.copy(self.mod.out_a)
+ m.d.comb += self.out_b.copy(self.mod.out_b)
+
+ self.a0mod.setup(m, self.out_a, self.out_b)
+ m.d.comb += self.a0_out_z.copy(self.a0mod.out_z)
+ m.d.comb += self.out_tot.eq(self.a0mod.out_tot)
+
+ self.a1mod.setup(m, self.out_tot, self.a0_out_z)
+
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ m.d.sync += self.out_of.copy(self.a1mod.out_of)
+ m.d.sync += self.out_z.copy(self.a1mod.out_z)
+ m.next = "normalise_1"
+
+
class FPAddStage0Mod:
def __init__(self, width):
self.out_z = FPNumBase(width, False)
self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.add0 = self
+ m.d.comb += self.in_a.copy(in_a)
+ m.d.comb += self.in_b.copy(in_b)
+
def elaborate(self, platform):
m = Module()
m.submodules.add0_in_a = self.in_a
def setup(self, m, in_a, in_b, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.add0 = self.mod
- m.d.comb += self.mod.in_a.copy(in_a)
- m.d.comb += self.mod.in_b.copy(in_b)
+ self.mod.setup(m, in_a, in_b)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
+ def setup(self, m, in_tot, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.add1 = self
+ m.submodules.add1_out_overflow = self.out_of
+
+ m.d.comb += self.in_z.copy(in_z)
+ m.d.comb += self.in_tot.eq(in_tot)
+
def elaborate(self, platform):
m = Module()
#m.submodules.norm1_in_overflow = self.in_of
def setup(self, m, in_tot, in_z, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.add1 = self.mod
- m.submodules.add1_out_overflow = self.out_of
-
- m.d.comb += self.mod.in_z.copy(in_z)
- m.d.comb += self.mod.in_tot.eq(in_tot)
+ self.mod.setup(m, in_tot, in_z)
m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
def __init__(self, width):
self.width = width
- self.in_select = Signal(reset_less=True)
self.out_norm = Signal(reset_less=True)
self.in_z = FPNumBase(width, False)
self.in_of = Overflow()
- self.temp_z = FPNumBase(width, False)
- self.temp_of = Overflow()
self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
+ def setup(self, m, in_z, in_of, out_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.normalise_1 = self
+
+ m.d.comb += self.in_z.copy(in_z)
+ m.d.comb += self.in_of.copy(in_of)
+
+ m.d.comb += out_z.copy(self.out_z)
+
def elaborate(self, platform):
m = Module()
m.submodules.norm1_out_z = self.out_z
m.submodules.norm1_out_overflow = self.out_of
- m.submodules.norm1_temp_z = self.temp_z
- m.submodules.norm1_temp_of = self.temp_of
m.submodules.norm1_in_z = self.in_z
m.submodules.norm1_in_overflow = self.in_of
msr = MultiShiftRMerge(mwid, espec)
m.submodules.multishift_r = msr
- # select which of temp or in z/of to use
- with m.If(self.in_select):
- m.d.comb += in_z.copy(self.in_z)
- m.d.comb += in_of.copy(self.in_of)
- with m.Else():
- m.d.comb += in_z.copy(self.temp_z)
- m.d.comb += in_of.copy(self.temp_of)
+ m.d.comb += in_z.copy(self.in_z)
+ m.d.comb += in_of.copy(self.in_of)
# initialise out from in (overridden below)
m.d.comb += self.out_z.copy(in_z)
m.d.comb += self.out_of.copy(in_of)
increase = Signal(reset_less=True)
m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
m.d.comb += increase.eq(in_z.exp_lt_n126)
- m.d.comb += self.out_norm.eq(0) # loop-end condition
# decrease exponent
with m.If(decrease):
# *sigh* not entirely obvious: count leading zeros (clz)
return m
-class FPNorm1(FPState, FPID):
+class FPNorm1Single(FPState, FPID):
def __init__(self, width, id_wid, single_cycle=True):
FPID.__init__(self, id_wid)
FPState.__init__(self, "normalise_1")
- if single_cycle:
- self.mod = FPNorm1ModSingle(width)
- else:
- self.mod = FPNorm1ModMulti(width)
+ self.mod = FPNorm1ModSingle(width)
+ self.out_norm = Signal(reset_less=True)
+ self.out_z = FPNumBase(width)
+ self.out_roundz = Signal(reset_less=True)
+
+ def setup(self, m, in_z, in_of, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.mod.setup(m, in_z, in_of, self.out_z)
+
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
+ m.next = "round"
+
+
+class FPNorm1Multi(FPState, FPID):
+
+ def __init__(self, width, id_wid):
+ FPID.__init__(self, id_wid)
+ FPState.__init__(self, "normalise_1")
+ self.mod = FPNorm1ModMulti(width)
self.stb = Signal(reset_less=True)
self.ack = Signal(reset=0, reset_less=True)
self.out_norm = Signal(reset_less=True)
def setup(self, m, in_z, in_of, norm_stb, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.normalise_1 = self.mod
-
- m.d.comb += self.mod.in_z.copy(in_z)
- m.d.comb += self.mod.in_of.copy(in_of)
-
- m.d.comb += self.mod.in_select.eq(self.in_accept)
- m.d.comb += self.mod.temp_z.copy(self.temp_z)
- m.d.comb += self.mod.temp_of.copy(self.temp_of)
-
- m.d.comb += self.out_z.copy(self.mod.out_z)
- m.d.comb += self.out_norm.eq(self.mod.out_norm)
+ self.mod.setup(m, in_z, in_of, norm_stb,
+ self.in_accept, self.temp_z, self.temp_of,
+ self.out_z, self.out_norm)
m.d.comb += self.stb.eq(norm_stb)
m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
+class FPNormToPack(FPState, FPID):
+
+ def __init__(self, width, id_wid):
+ FPID.__init__(self, id_wid)
+ FPState.__init__(self, "normalise_1")
+ self.width = width
+
+ def setup(self, m, in_z, in_of, in_mid):
+ """ links module to inputs and outputs
+ """
+
+ # Normalisation (chained to input in_z+in_of)
+ nmod = FPNorm1ModSingle(self.width)
+ n_out_z = FPNumBase(self.width)
+ n_out_roundz = Signal(reset_less=True)
+ nmod.setup(m, in_z, in_of, n_out_z)
+
+ # Rounding (chained to normalisation)
+ rmod = FPRoundMod(self.width)
+ r_out_z = FPNumBase(self.width)
+ rmod.setup(m, n_out_z, n_out_roundz)
+ m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
+ m.d.comb += r_out_z.copy(rmod.out_z)
+
+ # Corrections (chained to rounding)
+ cmod = FPCorrectionsMod(self.width)
+ c_out_z = FPNumBase(self.width)
+ cmod.setup(m, r_out_z)
+ m.d.comb += c_out_z.copy(cmod.out_z)
+
+ # Pack (chained to corrections)
+ self.pmod = FPPackMod(self.width)
+ self.out_z = FPNumBase(self.width)
+ self.pmod.setup(m, c_out_z)
+
+ # Multiplex ID
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m) # copies incoming ID to outgoing
+ m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
+ m.next = "pack_put_z"
+
+
class FPRoundMod:
def __init__(self, width):
self.in_z = FPNumBase(width, False)
self.out_z = FPNumBase(width, False)
+ def setup(self, m, in_z, roundz):
+ m.submodules.roundz = self
+
+ m.d.comb += self.in_z.copy(in_z)
+ m.d.comb += self.in_roundz.eq(roundz)
+
def elaborate(self, platform):
m = Module()
m.d.comb += self.out_z.copy(self.in_z)
def setup(self, m, in_z, roundz, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.roundz = self.mod
+ self.mod.setup(m, in_z, roundz)
- m.d.comb += self.mod.in_z.copy(in_z)
- m.d.comb += self.mod.in_roundz.eq(roundz)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
self.in_z = FPNumOut(width, False)
self.out_z = FPNumOut(width, False)
+ def setup(self, m, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.corrections = self
+ m.d.comb += self.in_z.copy(in_z)
+
def elaborate(self, platform):
m = Module()
m.submodules.corr_in_z = self.in_z
def setup(self, m, in_z, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.corrections = self.mod
- m.d.comb += self.mod.in_z.copy(in_z)
+ self.mod.setup(m, in_z)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
self.in_z = FPNumOut(width, False)
self.out_z = FPNumOut(width, False)
+ def setup(self, m, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.pack = self
+ m.d.comb += self.in_z.copy(in_z)
+
def elaborate(self, platform):
m = Module()
m.submodules.pack_in_z = self.in_z
def setup(self, m, in_z, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.pack = self.mod
- m.d.comb += self.mod.in_z.copy(in_z)
+ self.mod.setup(m, in_z)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
class FPPutZ(FPState):
- def __init__(self, state, in_z, out_z, in_mid, out_mid):
+ def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
FPState.__init__(self, state)
+ if to_state is None:
+ to_state = "get_ops"
+ self.to_state = to_state
self.in_z = in_z
self.out_z = out_z
self.in_mid = in_mid
]
with m.If(self.out_z.stb & self.out_z.ack):
m.d.sync += self.out_z.stb.eq(0)
- m.next = "get_ops"
+ m.next = self.to_state
with m.Else():
m.d.sync += self.out_z.stb.eq(1)
+class FPPutZIdx(FPState):
+
+ def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
+ FPState.__init__(self, state)
+ if to_state is None:
+ to_state = "get_ops"
+ self.to_state = to_state
+ self.in_z = in_z
+ self.out_zs = out_zs
+ self.in_mid = in_mid
+
+ def action(self, m):
+ outz_stb = Signal(reset_less=True)
+ outz_ack = Signal(reset_less=True)
+ m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
+ outz_ack.eq(self.out_zs[self.in_mid].ack),
+ ]
+ m.d.sync += [
+ self.out_zs[self.in_mid].v.eq(self.in_z.v)
+ ]
+ with m.If(outz_stb & outz_ack):
+ m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
+ m.next = self.to_state
+ with m.Else():
+ m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
+
+
class FPADDBaseMod(FPID):
def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
- n1 = self.add_state(FPNorm1(self.width, self.id_wid))
- n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
+ if self.single_cycle:
+ n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
+ n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
+ else:
+ n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
+ n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
rn = self.add_state(FPRound(self.width, self.id_wid))
rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
a = get.out_op1
b = get.out_op2
- sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
+ sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
sc.setup(m, a, b, self.in_mid)
- dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
- dn.setup(m, a, b, sc.in_mid)
-
- if self.single_cycle:
- alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
- alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
- else:
- alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
- alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
-
- add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
- add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
-
- add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
- add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
-
- n1 = self.add_state(FPNorm1(self.width, self.id_wid))
- n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
-
- rn = self.add_state(FPRound(self.width, self.id_wid))
- rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
-
- cor = self.add_state(FPCorrections(self.width, self.id_wid))
- cor.setup(m, rn.out_z, rn.in_mid)
+ alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
+ alm.setup(m, sc.out_a, sc.out_b, sc.in_mid)
- pa = self.add_state(FPPack(self.width, self.id_wid))
- pa.setup(m, cor.out_z, rn.in_mid)
+ n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
+ n1.setup(m, alm.out_z, alm.out_of, alm.in_mid)
- ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
- pa.in_mid, self.out_mid))
+ ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
+ n1.in_mid, self.out_mid))
pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
- pa.in_mid, self.out_mid))
+ sc.in_mid, self.out_mid))
class FPADDBase(FPState, FPID):
m.d.sync += self.add_stb.eq(add_stb)
m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
+ m.d.sync += self.out_z.ack.eq(0) # likewise
#m.d.sync += self.in_t.stb.eq(0)
m.submodules.fpadd = self.mod
with m.Else():
m.d.sync += [self.add_ack.eq(0),
self.in_t.stb.eq(0),
+ self.out_z.ack.eq(1),
]
with m.Else():
# done: acknowledge, and write out id and value
m.d.sync += [self.add_ack.eq(1),
self.in_t.stb.eq(0)
]
- m.next = "get_a"
+ m.next = "put_z"
return
with m.Else():
m.d.sync += self.out_z.stb.eq(1)
+class ResArray:
+ def __init__(self, width, id_wid):
+ self.width = width
+ self.id_wid = id_wid
+ res = []
+ for i in range(rs_sz):
+ out_z = FPOp(width)
+ out_z.name = "out_z_%d" % i
+ res.append(out_z)
+ self.res = Array(res)
+ self.in_z = FPOp(width)
+ self.in_mid = Signal(self.id_wid, reset_less=True)
+
+ def setup(self, m, in_z, in_mid):
+ m.d.comb += [self.in_z.copy(in_z),
+ self.in_mid.eq(in_mid)]
+
+ def get_fragment(self, platform=None):
+ """ creates the HDL code-fragment for FPAdd
+ """
+ m = Module()
+ m.submodules.res_in_z = self.in_z
+ m.submodules += self.res
+
+ return m
+
+ def ports(self):
+ res = []
+ for z in self.res:
+ res += z.ports()
+ return res
+
class FPADD(FPID):
""" FPADD: stages as follows:
needs to be the thing that raises the incoming stb.
"""
- def __init__(self, width, id_wid=None, single_cycle=False):
+ def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
""" IEEE754 FP Add
* width: bit-width of IEEE754. supported: 16, 32, 64
* id_wid: an identifier that is sync-connected to the input
* single_cycle: True indicates each stage to complete in 1 clock
"""
- FPID.__init__(self, id_wid)
self.width = width
self.id_wid = id_wid
self.single_cycle = single_cycle
- self.in_a = FPOp(width)
- self.in_b = FPOp(width)
- self.out_z = FPOp(width)
+ #self.out_z = FPOp(width)
+ self.ids = FPID(id_wid)
+
+ rs = []
+ for i in range(rs_sz):
+ in_a = FPOp(width)
+ in_b = FPOp(width)
+ in_a.name = "in_a_%d" % i
+ in_b.name = "in_b_%d" % i
+ rs.append((in_a, in_b))
+ self.rs = Array(rs)
+
+ res = []
+ for i in range(rs_sz):
+ out_z = FPOp(width)
+ out_z.name = "out_z_%d" % i
+ res.append(out_z)
+ self.res = Array(res)
self.states = []
""" creates the HDL code-fragment for FPAdd
"""
m = Module()
- m.submodules.in_a = self.in_a
- m.submodules.in_b = self.in_b
- m.submodules.out_z = self.out_z
+ m.submodules += self.rs
+
+ in_a = self.rs[0][0]
+ in_b = self.rs[0][1]
+
+ out_z = FPOp(self.width)
+ out_mid = Signal(self.id_wid, reset_less=True)
+ m.submodules.out_z = out_z
geta = self.add_state(FPGetOp("get_a", "get_b",
- self.in_a, self.width))
- geta.setup(m, self.in_a)
+ in_a, self.width))
+ geta.setup(m, in_a)
a = geta.out_op
getb = self.add_state(FPGetOp("get_b", "fpadd",
- self.in_b, self.width))
- getb.setup(m, self.in_b)
+ in_b, self.width))
+ getb.setup(m, in_b)
b = getb.out_op
ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
ab = self.add_state(ab)
- ab.setup(m, a, b, getb.out_decode, self.in_mid,
- self.out_z, self.out_mid)
+ ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
+ out_z, out_mid)
- #pz = self.add_state(FPPutZ("put_z", ab.out_z, self.out_z,
- # ab.out_mid, self.out_mid))
+ pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
+ out_mid, "get_a"))
with m.FSM() as fsm:
if __name__ == "__main__":
if True:
alu = FPADD(width=32, id_wid=5, single_cycle=True)
- main(alu, ports=alu.in_a.ports() + \
- alu.in_b.ports() + \
- alu.out_z.ports() + \
- [alu.in_mid, alu.out_mid])
+ main(alu, ports=alu.rs[0][0].ports() + \
+ alu.rs[0][1].ports() + \
+ alu.res[0].ports() + \
+ [alu.ids.in_mid, alu.ids.out_mid])
else:
alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
main(alu, ports=[alu.in_a, alu.in_b] + \
projects / ieee754fpu.git / blobdiff