add (but comment out) reset signal

[ieee754fpu.git] / src / add / test_add.py

diff --git a/src/add/test_add.py b/src/add/test_add.py
index 8363279ce0965800603c7698ba31a02c9a8fbe1f..d63c26f1241f35771bb37852d3058c57490fe91d 100644 (file)
--- a/src/add/test_add.py
+++ b/src/add/test_add.py
@@ -11,6 +11,10 @@ from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
                                 run_edge_cases, run_corner_cases)
 
 def testbench(dut):
+    yield from check_case(dut, 0x36093399, 0x7f6a12f1, 0x7f6a12f1)
+    yield from check_case(dut, 0x006CE3EE, 0x806CE3EC, 0x00000002)
+    yield from check_case(dut, 0x00000047, 0x80000048, 0x80000001)
+    yield from check_case(dut, 0x000116C2, 0x8001170A, 0x80000048)
     yield from check_case(dut, 0x7ed01f25, 0xff559e2c, 0xfedb1d33)
     yield from check_case(dut, 0, 0, 0)
     yield from check_case(dut, 0xFFFFFFFF, 0xC63B800A, 0x7FC00000)
@@ -69,6 +73,6 @@ def testbench(dut):
     yield from run_edge_cases(dut, count, add)
 
 if __name__ == '__main__':
-    dut = FPADD(width=32, single_cycle=True)
+    dut = FPADD(width=32, id_wid=5, single_cycle=True)
     run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")