add (but comment out) reset signal

[ieee754fpu.git] / src / add / test_dual.py

diff --git a/src/add/test_dual.py b/src/add/test_dual.py
index 55facb12653425b7a609b7348b82a22a740f5c45..15f5c762df9a2e78ede74c8725c3806a022cc2ef 100644 (file)
--- a/src/add/test_dual.py
+++ b/src/add/test_dual.py
@@ -4,13 +4,6 @@ from dual_add_experiment import ALU
 
 
 def get_case(dut, a, b, c):
-    yield dut.c.v.eq(c)
-    yield dut.c.stb.eq(1)
-    yield
-    yield
-    c_ack = (yield dut.c.ack)
-    assert c_ack == 0
-
     yield dut.a.v.eq(a)
     yield dut.a.stb.eq(1)
     yield
@@ -18,6 +11,8 @@ def get_case(dut, a, b, c):
     a_ack = (yield dut.a.ack)
     assert a_ack == 0
 
+    yield dut.a.stb.eq(0)
+
     yield dut.b.v.eq(b)
     yield dut.b.stb.eq(1)
     yield
@@ -25,23 +20,28 @@ def get_case(dut, a, b, c):
     b_ack = (yield dut.b.ack)
     assert b_ack == 0
 
+    yield dut.b.stb.eq(0)
+
+    yield dut.c.v.eq(c)
+    yield dut.c.stb.eq(1)
+    yield
+    yield
+    c_ack = (yield dut.c.ack)
+    assert c_ack == 0
+
+    yield dut.c.stb.eq(0)
+
+    yield dut.z.ack.eq(1)
+
     while True:
-        yield
         out_z_stb = (yield dut.z.stb)
         if not out_z_stb:
+            yield
             continue
 
         out_z = yield dut.z.v
 
-        yield dut.z.ack.eq(1)
-        yield dut.a.stb.eq(0)
-        yield dut.b.stb.eq(0)
-        yield dut.c.stb.eq(0)
-        yield
-        yield
         yield dut.z.ack.eq(0)
-        yield
-        yield
         break
 
     return out_z